【摘要】：隨著數(shù)據(jù)通信技術(shù)與網(wǎng)絡(luò)技術(shù)的發(fā)展,數(shù)據(jù)信息網(wǎng)分布越來越廣泛。網(wǎng)絡(luò)數(shù)據(jù)通信有其特有的復(fù)雜性。網(wǎng)絡(luò)中的每條通信鏈路都同時通過多種通信設(shè)備,一旦發(fā)生故障,很難分清故障發(fā)生點。需要專業(yè)檢測人員逐個通過軟件進行現(xiàn)場排查,才能確定整個鏈路中的哪些設(shè)備出現(xiàn)問題。這種排查方法造成了檢測人員工作量大,重復(fù)性工作多等問題,而且測試工作效率低,對維護人員的技術(shù)要求高,不能正確診斷故障原因并進行誤碼分析。誤碼測試儀能很好的協(xié)助解決上述問題。 市面上的誤碼儀功能齊全,但普遍體積偏大,使用不方便且價格昂貴。本文設(shè)計和實現(xiàn)了一種基于嵌入式Linux系統(tǒng)的便攜式低速異步環(huán)回誤碼測試儀。本設(shè)計采用三星公司的S3C2440芯片作為主控制器,協(xié)同DS2172專用誤碼芯片、SP505串行接口芯片、LXT360E1接口芯片及Cyclonell FPGA可編程邏輯器件共同完成誤碼儀功能,并通過Linux命令行進行結(jié)果顯示及人機交互。 本誤碼測試儀可以完成一般誤碼測試、HDLC誤碼測試、E1誤碼測試以及專用的業(yè)務(wù)仿真誤碼測試。誤碼測試最高速率可達到2Mbps,提供多種偽隨機碼和人工碼。本文詳細介紹了具體的軟硬件設(shè)計,包括嵌入式Linux底層驅(qū)動的開發(fā)、邏輯接口功能設(shè)計、誤碼比對模塊設(shè)計、用戶界面實現(xiàn)以及測試結(jié)果管理,并對設(shè)計結(jié)果進行了系統(tǒng)驗證,表明該誤碼儀可以完成誤碼測試,滿足系統(tǒng)數(shù)據(jù)傳輸中常見故障檢測需求。
[Abstract]:With the development of data communication technology and network technology, data information network is more and more widely distributed. Network data communication has its unique complexity. Each communication link in the network passes through a variety of communication devices at the same time. Once a fault occurs, it is difficult to distinguish the fault point. In order to determine which equipment is wrong in the whole link, it is necessary for the professional examiner to carry out the spot check one by one through the software. This method causes many problems such as heavy workload and repetitive work, low efficiency of test work, high technical requirements for maintainers, unable to correctly diagnose the causes of faults and carry out error code analysis. Error code tester can help solve the above problems. The BER on the market has a complete range of functions, but it is generally large, inconvenient and expensive to use. A portable low speed asynchronous loop error tester based on embedded Linux system is designed and implemented in this paper. In this design, the S3C2440 chip of Samsung Company is used as the main controller, and the function of the error-meter is completed in cooperation with the DS2172 special error-code chip, the SP505 serial interface chip, the LXT360E1 interface chip and the Cyclonell FPGA programmable logic device. And through the Linux command line to display the results and man-machine interaction. The BER tester can complete general error test, HDLC error test, E1 error test and special service simulation error code test. The maximum rate of error test can reach 2 Mbps. it provides a variety of pseudorandom codes and manual codes. This paper introduces the design of hardware and software in detail, including the development of embedded Linux bottom driver, the function design of logic interface, the design of BER module, the realization of user interface and the management of test results. The result shows that the error detector can complete the error test and meet the common fault detection requirements in the system data transmission.
【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TN402;TP368.1

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