【摘要】：隨著通信行業(yè)的飛速發(fā)展,數(shù)據(jù)傳輸?shù)乃俣纫笠苍絹?lái)越高。原先的480Mbps的USB2.0傳輸速度已經(jīng)不能滿(mǎn)足數(shù)據(jù)傳輸?shù)男枨?于是傳輸速度5Gbps的 USB3.0 應(yīng)運(yùn)而生。USB3.0 Promoter Group 是由微軟、惠普、Intel、NEC、ST-NXP、德州儀器等IT行業(yè)巨頭組成的,該組織于2008年宣布制定的新一代USB3.0標(biāo)準(zhǔn)已經(jīng)順利完成并且公開(kāi)發(fā)布了。USB3.0無(wú)論在傳輸速度還是在性能方面都有非常大的提升。論文詳細(xì)介紹了 USB3.0物理層數(shù)字電路模塊的劃分以及相應(yīng)模塊的的原理,功能和詳細(xì)的電路設(shè)計(jì),最后運(yùn)用Verilog硬件語(yǔ)言編寫(xiě)相應(yīng)代碼,并完成功能仿真。論文研究IEEE指定的USB3.0的詳細(xì)標(biāo)準(zhǔn)規(guī)范,主要針對(duì)第六章物理層的相關(guān)知識(shí)進(jìn)行學(xué)習(xí)和研究。并在研究的過(guò)程中對(duì)數(shù)字模塊進(jìn)行電路設(shè)計(jì),首先對(duì)于物理層和數(shù)字鏈路層數(shù)據(jù)傳輸進(jìn)行分析,然后具體對(duì)8B/10B編碼器和解碼器模塊,K28.5檢測(cè)模塊,接收狀態(tài)檢測(cè)模塊,彈性緩沖器模塊進(jìn)行數(shù)字電路設(shè)計(jì),最后運(yùn)用Verilog硬件語(yǔ)言描述,運(yùn)用QuatursⅡ開(kāi)發(fā)工具進(jìn)行功能仿真。論文依據(jù)USB3.0標(biāo)準(zhǔn)規(guī)范,基于FPGA分別按要求實(shí)現(xiàn)各個(gè)模塊的數(shù)字電路設(shè)計(jì)。仿真結(jié)果顯示基本能夠完成目標(biāo)要求。
[Abstract]:With the rapid development of the communication industry, the speed of data transmission is higher and higher. The USB2.0 transmission speed of the original 480Mbps can no longer meet the demand of data transmission, so the USB3.0 of the transmission speed 5Gbps came into being. USB3.0 Promoter Group is composed of IT giants such as Microsoft, HP, Intel,NEC,ST-NXP, Texas Instruments, etc. The group announced in 2008 that a new generation of USB3.0 standards had been successfully completed and publicly released. USB3.0 has made significant improvements in both speed and performance. The paper introduces the division of the USB3.0 physical layer digital circuit module, the principle of the corresponding module, the function and the detailed circuit design in detail. Finally, the corresponding code is compiled by using the Verilog hardware language, and the functional simulation is completed. This paper studies the detailed standard specification of USB3.0 specified by IEEE, and mainly studies the related knowledge of physical layer in Chapter 6. In the process of research, the circuit design of digital module is carried out. Firstly, the data transmission of physical layer and digital link layer is analyzed, then the 8B/10B encoder and decoder module, K28.5 detection module, receiving status detection module are concretely analyzed. The elastic buffer module is used to design the digital circuit. Finally, the Verilog hardware language is used to describe the function and the Quaturs 鈪，

本文編號(hào)：2336830