【摘要】：隨著PLC應(yīng)用的迅速發(fā)展,PLC對(duì)處理器的要求也隨之不斷提高。PLC需要處理器像商用處理器那樣越來(lái)越廉價(jià),像DSP處理器那樣數(shù)據(jù)處理能力越來(lái)越強(qiáng),特別是需要處理器具備工業(yè)應(yīng)用現(xiàn)場(chǎng)上的實(shí)時(shí)處理性能。本文對(duì)現(xiàn)有PLC及其處理器的發(fā)展現(xiàn)狀、發(fā)展方向、工作方式、工作需求進(jìn)行了大量的研究和分析,在此基礎(chǔ)上,設(shè)計(jì)了一款針對(duì)于PLC應(yīng)用的實(shí)時(shí)性高效率的處理器——基于狀態(tài)機(jī)的PLC處理器。經(jīng)過(guò)研究,筆者在本文中提出了高效率處理器理念和狀態(tài)機(jī)群理念,并將狀態(tài)機(jī)群理念作為本論文的創(chuàng)新點(diǎn)。高效率處理器理念就是,以盡量少的程序代碼完成盡量多的數(shù)據(jù)處理,其具體描述指標(biāo)是MDPS(Millions of Data Per Second,每秒多少百萬(wàn)數(shù)據(jù))和DIR(Data Instructions Ratio,數(shù)據(jù)指令比);狀態(tài)機(jī)群理念就是通過(guò)主狀態(tài)機(jī)-從狀態(tài)機(jī)的狀態(tài)機(jī)群來(lái)實(shí)現(xiàn)較為復(fù)雜而重復(fù)的具體的數(shù)據(jù)處理操作(8051單片機(jī)的SFR部分,就是CPU控制下的一種可配置狀態(tài)機(jī)群);避免重復(fù)取指令造成的總線占用,以獲得比RISC更高的數(shù)據(jù)處理效率,比DSP更高的靈活性;通過(guò)數(shù)組加法和鏈表搜索的算例作了具體的詳細(xì)解釋。本文完成了基于狀態(tài)機(jī)的PLC處理器的如下設(shè)計(jì):處理器架構(gòu)設(shè)計(jì)(操作集成的數(shù)組加法和鏈表搜索);指令系統(tǒng)設(shè)計(jì)(程序計(jì)數(shù)器設(shè)計(jì)、取指令操作設(shè)計(jì)、指令集設(shè)計(jì)、指令碼設(shè)計(jì)、特殊功能寄存器設(shè)計(jì));并且運(yùn)用Verilog HDL硬件描述語(yǔ)言編程實(shí)現(xiàn)了,主從狀態(tài)機(jī)、狀態(tài)機(jī)群、狀態(tài)機(jī)群的存儲(chǔ)器、狀態(tài)機(jī)處理器指令等。其中狀態(tài)機(jī)處理器指令的Verilog實(shí)現(xiàn)包括:通用指令的實(shí)現(xiàn)、狀態(tài)機(jī)群指令的實(shí)現(xiàn)、數(shù)組加法及鏈表搜索的實(shí)現(xiàn)、特殊功能的實(shí)現(xiàn)。并且利用Modelsim SE軟件,結(jié)合FPGA技術(shù),對(duì)基于狀態(tài)機(jī)的PLC處理器的尋址方式、通用指令、狀態(tài)機(jī)群、定時(shí)器、中斷、數(shù)組加法及鏈表搜索進(jìn)行邏輯功能的仿真驗(yàn)證,仿真結(jié)果證明了基于狀態(tài)機(jī)的PLC處理器的可行性。
[Abstract]:With the rapid development of PLC applications, the requirements of PLC for processors are increasing. PLC requires processors to be as cheap as commercial processors, and data processing capabilities like DSP processors are becoming stronger and stronger. In particular, the processor is required to have real-time processing performance on the industrial application field. This paper has carried on the massive research and the analysis to the present PLC and its processor development present situation, the development direction, the working way, the work demand, on this basis, A real-time and efficient processor for PLC application is designed, which is based on state machine based PLC processor. Through research, the author puts forward the idea of high efficiency processor and state cluster, and takes the concept of state machine cluster as the innovation of this paper. The idea of an efficient processor is to do as much data processing as possible with as little program code as possible, the specification of which is how many millions of MDPS (Millions of Data Per Second, data per second) and the DIR (Data Instructions Ratio, data instruction ratio). The concept of state cluster is to realize complex and repeated data processing operations through the state cluster of master state machine and slave state machine (the SFR part of 8051 single chip microcomputer is a configurable state cluster under CPU control); In order to obtain higher data processing efficiency than RISC and more flexibility than DSP, the bus footprint caused by repeated fetching instructions is avoided. The examples of array addition and linked list search are explained in detail. In this paper, the state machine based PLC processor is designed as follows: processor architecture design (operation integrated array addition and list search); Instruction system design (program counter design, instruction operation design, instruction set design, instruction code design, special function register design); And the Verilog HDL hardware description language is used to realize the master-slave state machine, the memory of the state machine group, the state machine processor instruction and so on. The Verilog implementation of state machine processor instruction includes the realization of general instruction, the realization of state cluster instruction, the realization of array addition and chain list search, and the realization of special function. Using Modelsim SE software and FPGA technology, the logic function of PLC processor based on state machine, general instruction, state cluster, timer, interrupt, array addition and chain list search are simulated. The simulation results show the feasibility of the state machine based PLC processor.
【學(xué)位授予單位】：沈陽(yáng)理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP332

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