【摘要】：作為現(xiàn)代電子系統(tǒng)的核心，微處理器往往在電子系統(tǒng)的電磁兼容中扮演著重要角色。隨著集成電路制造工藝的不斷進步，特征尺寸的不斷減小，微處理器的工作頻率和集成度越來越高、工作電壓越來越低，，對外界電磁干擾越來越敏感。出于系統(tǒng)設計人員對集成電路電磁兼容性的要求，迫切的需要研究微處理器電快速瞬變脈沖群（EFT）測試方法來衡量微處理器對EFT干擾的抗擾度性能，并開展相應的微處理器片上EFT防護設計研究以提高微處理器的EFT抗擾度。本文正是針對這種需求，在分析系統(tǒng)級EFT測試方法和總結現(xiàn)有集成電路瞬態(tài)抗擾度測試方案的基礎上，實現(xiàn)了一種微處理器EFT測試方法，并對相應的微處理器片上EFT防護設計的Trigger電路展開了研究。 第一部分實現(xiàn)了一種微處理器EFT測試方法。首先對系統(tǒng)級EFT測試方法展開研究，分析了系統(tǒng)級EFT干擾對微處理器的危害及其作用機理。然后對目前集成電路級瞬態(tài)脈沖抗擾度測試的幾種可行方案進行分析與對比。最后確定了本文所采用的方案，從測試環(huán)境設置、測試硬件設計、測試軟件設計以及測試流程等幾方面進行了詳細論述。 第二部分通過測試案例對測試方法的性能展開研究。主要選取了一款微處理器芯片進行了實際測試，通過對測試案例結果的分析，總結了測試過程中發(fā)現(xiàn)的問題，對微處理器EFT測試過程中出現(xiàn)的幾種失效模式及機理進行了相應的研究，并通過實驗對測試結果的重復性和重現(xiàn)性問題進行了深入研究。 第三部分對微處理器片上EFT防護設計的Trigger電路展開了研究。根據(jù)對EFT防護電路性能要求的分析，結合微處理器片上ESD防護電路結構，提出了一種EFT Trigger電路，利用片上ESD保護電路實現(xiàn)對EFT干擾的防護，并通過仿真分析以及實際測試對該防護電路的性能進行了驗證。
[Abstract]:As the core of modern electronic system, microprocessor often plays an important role in electromagnetic compatibility of electronic system. With the development of integrated circuit manufacturing technology and the decrease of characteristic size, the working frequency and integration of microprocessors are higher and higher, the working voltage is lower and lower, and they are more sensitive to external electromagnetic interference (EMI). In order to meet the requirements of the system designers for the electromagnetic compatibility of integrated circuits, it is urgent to study the (EFT) test method of the microprocessor electric fast transient pulse group to measure the immunity of the microprocessor to EFT interference. In order to improve the EFT immunity of microprocessor, the corresponding design of EFT protection on chip is carried out. In this paper, a microprocessor EFT testing method is implemented on the basis of analyzing system-level EFT test methods and summarizing the existing IC transient immunity test schemes. The Trigger circuit designed for EFT protection is studied. In the first part, a microprocessor EFT testing method is implemented. Firstly, the system-level EFT testing method is studied, and the harm of system-level EFT interference to microprocessor and its mechanism are analyzed. Then several feasible schemes of IC transient pulse immunity test are analyzed and compared. Finally, the scheme of this paper is determined, including the setting of test environment, the design of test hardware, the design of test software and the test flow. In the second part, the performance of the test method is studied through test cases. A microprocessor chip is selected for practical test. Through the analysis of test cases, the problems found in the testing process are summarized. Several failure modes and mechanisms in the process of microprocessor EFT testing are studied, and the repeatability and reproducibility of the test results are studied through experiments. In the third part, the Trigger circuit designed for EFT protection on microprocessor chip is studied. Based on the analysis of the performance requirements of EFT protection circuit and combined with the structure of ESD protection circuit on microprocessor chip, a EFT Trigger circuit is proposed to protect EFT from interference by using on-chip ESD protection circuit. The performance of the protective circuit is verified by simulation analysis and actual test.
【學位授予單位】：湘潭大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP332

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