任意點存儲器結(jié)構(gòu)FFT處理器地址策略
發(fā)布時間：2018-11-07 16:54
【摘要】：提出一種針對任意點數(shù)運算的并行地址無沖突的存儲器結(jié)構(gòu)的FFT處理器.該方法利用高基底的分解方法減少整體計算時鐘周期,以及小基底互聯(lián)的多路延遲交換結(jié)構(gòu)降低計算引擎的復(fù)雜度.該方法可以將存儲器結(jié)構(gòu)FFT處理器中的幾個重要特性如連續(xù)幀處理模式,多點數(shù)計算和并行無地址沖突等特點集成在一起.另外,素因子FFT算法也被運用到該處理器當(dāng)中用以降低乘法器個數(shù)和蝶形因子存儲,以及滿足任意點數(shù)的計算需求.設(shè)計了一種統(tǒng)一的基-2,3,4,5的Winograd算法的蝶形計算單元用以降低計算復(fù)雜度.實驗仿真結(jié)果表明,本FFT處理器在122.88MHz工作頻率下功耗只有40.8mW,非常適合LTE系統(tǒng)的應(yīng)用.
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者單位】： 中國科學(xué)院微電子研究所;
【分類號】：TP332;TP333
本文編號：2316970
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者單位】： 中國科學(xué)院微電子研究所;
【分類號】：TP332;TP333
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