任意點(diǎn)存儲(chǔ)器結(jié)構(gòu)FFT處理器地址策略
發(fā)布時(shí)間：2018-11-07 16:54
【摘要】：提出一種針對(duì)任意點(diǎn)數(shù)運(yùn)算的并行地址無(wú)沖突的存儲(chǔ)器結(jié)構(gòu)的FFT處理器.該方法利用高基底的分解方法減少整體計(jì)算時(shí)鐘周期,以及小基底互聯(lián)的多路延遲交換結(jié)構(gòu)降低計(jì)算引擎的復(fù)雜度.該方法可以將存儲(chǔ)器結(jié)構(gòu)FFT處理器中的幾個(gè)重要特性如連續(xù)幀處理模式,多點(diǎn)數(shù)計(jì)算和并行無(wú)地址沖突等特點(diǎn)集成在一起.另外,素因子FFT算法也被運(yùn)用到該處理器當(dāng)中用以降低乘法器個(gè)數(shù)和蝶形因子存儲(chǔ),以及滿足任意點(diǎn)數(shù)的計(jì)算需求.設(shè)計(jì)了一種統(tǒng)一的基-2,3,4,5的Winograd算法的蝶形計(jì)算單元用以降低計(jì)算復(fù)雜度.實(shí)驗(yàn)仿真結(jié)果表明,本FFT處理器在122.88MHz工作頻率下功耗只有40.8mW,非常適合LTE系統(tǒng)的應(yīng)用.
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者單位】： 中國(guó)科學(xué)院微電子研究所;
【分類號(hào)】：TP332;TP333
本文編號(hào)：2316970
[Abstract]:This paper presents a memory architecture FFT processor for any number of parallel addresses. In this method, the decomposition method of high substrate is used to reduce the overall computing clock cycle and the complexity of the computing engine is reduced by the multi-channel delay switching structure of the small substrate interconnection. This method can integrate several important features of memory architecture FFT processor, such as continuous frame processing mode, multi-point computation and parallel address-free collision. In addition, the prime factor FFT algorithm is also applied to the processor to reduce the number of multipliers and the storage of butterfly factors, and to meet the calculation requirements of arbitrary points. In this paper, a butterfly computing unit of a unified base-2 / 3 / 4 / 5 Winograd algorithm is designed to reduce the computational complexity. The simulation results show that the power consumption of the FFT processor is only 40.8 MW at the 122.88MHz operating frequency, which is very suitable for the application of LTE system.
【作者單位】： 中國(guó)科學(xué)院微電子研究所;
【分類號(hào)】：TP332;TP333
【相似文獻(xiàn)】
相關(guān)期刊論文 前2條
1 張?bào)镁?錢建平;;基于FPGA的級(jí)聯(lián)結(jié)構(gòu)FFT處理器的優(yōu)化設(shè)計(jì)[J];現(xiàn)代電子技術(shù);2009年22期
2 趙忠武,陳禾,韓月秋;基于FPGA的32位浮點(diǎn)FFT處理器的設(shè)計(jì)[J];電訊技術(shù);2003年06期
相關(guān)會(huì)議論文 前2條
1 李天悅;何晶;許信玉;;3780點(diǎn)FFT處理器結(jié)構(gòu)的研究[A];2011年通信與信息技術(shù)新進(jìn)展——第八屆中國(guó)通信學(xué)會(huì)學(xué)術(shù)年會(huì)論文集[C];2011年
2 李紅軍;姜嬌蕊;;自定制精度浮點(diǎn)FFT處理器的FPGA實(shí)現(xiàn)[A];全國(guó)第一屆嵌入式技術(shù)聯(lián)合學(xué)術(shù)會(huì)議論文集[C];2006年
相關(guān)碩士學(xué)位論文 前1條
1 崔振;地面數(shù)字電視廣播系統(tǒng)中SRRC濾波器及FFT處理器的設(shè)計(jì)與FPGA實(shí)現(xiàn)[D];北京郵電大學(xué);2009年
，本文編號(hào)：2316970
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2316970.html
最近更新
教材專著
