FT-DSPx RapidIO接口AMBA-SRIO橋的設計與實現(xiàn)
發(fā)布時間：2018-11-06 13:19
【摘要】：隨著超大規(guī)模集成電路的迅猛發(fā)展，數(shù)字信號處理器性能不斷提高，當前更是向著多核方向不斷發(fā)展，但總線傳輸性能的增長卻遠遠落后，系統(tǒng)互連傳輸能力成為嵌入式系統(tǒng)性能提升的瓶頸。在技術(shù)和市場的推動下，國際標準組織（ISO）和國際電工委員會（IEC）在2003年10月推出了專門針對嵌入式系統(tǒng)互連的國際標準——RapidIO(Rapid Input Output Interface)。RapidIO互連規(guī)范面向背板、片間互連通信，因具有較低的功耗和硬件成本優(yōu)勢，使其成為嵌入式互連的最佳選擇。 國防科技大學計算機學院微電子所研制的高性能數(shù)字信號處理器FT-DSPx是一款多核處理器。FT-DSPx集成了支持RapidIO1.3協(xié)議規(guī)范的兩個串行RapidIO（SRIO）模塊用于芯片間互連通信，使用ARM公司的片上總線協(xié)議AMBA3.0AXI接口把SRIO和DSP內(nèi)核進行連接。為了滿足FT-DSPx的互連需求，本文設計了RapidIO協(xié)議和AXI協(xié)議轉(zhuǎn)換的橋接部件AMBA-SRIO橋。本文主要工作包括： 1.本文首先系統(tǒng)研究了RapidIO1.3協(xié)議規(guī)范，分析了RapidIO互連協(xié)議架構(gòu)，對RapidIO邏輯層、傳輸層、物理層分別進行了研究分析。在分析FT-DSPx系統(tǒng)互連需求的基礎上，給出了SRIO的整體設計方案。 2.由于DSP內(nèi)部使用AMBA3.0AXI接口把SRIO和DSP內(nèi)核進行連接，因此在系統(tǒng)研究AMBA3.0總線協(xié)議規(guī)范的基礎上，設計了用于AXI協(xié)議和RapidIO協(xié)議轉(zhuǎn)換的AMBA-SRIO橋。借鑒GRIO ULI Interface，本文給出AMBA-SRIO橋與SRIO協(xié)議層模塊間的接口信號，包括輸入通道信號和輸出通道信號，完成了AMBA-SRIO橋與AXI接口信號和SRIO協(xié)議層信號的對接。 3.對AMBA-SRIO橋的功能模塊，包括控制和狀態(tài)寄存器配置、地址和事務映射邏輯、打包解包模塊和異步對接模塊進行了詳細設計與實現(xiàn)。重點對地址和事務映射機制、打包解包過程和利用格雷碼異步FIFO實現(xiàn)異步對接進行設計闡述。 4.對本文設計的AMBA-SRIO橋進行模塊級、部件級和芯片級驗證，重點對芯片級驗證進行了闡述，給出了驗證結(jié)果并予以分析。結(jié)果表明，集成AMBA-SRIO橋的SRIO能夠滿足協(xié)議規(guī)范定義的I/O邏輯操作和門鈴事務，并可以支持DMA操作，進一步驗證了本文所設計的AMBA-SRIO橋接部件可以滿足FT-DSPx互連需求。最后給出了邏輯綜合結(jié)果，，基于Synopsys公司65nm標準單元庫，設定溫度為25℃，工作電壓1.2V條件下，面積為109.4051μm2，功耗為10.1024mw。
[Abstract]:With the rapid development of VLSI, the performance of digital signal processor (DSP) has been improved, especially towards multi-core, but the increase of bus transmission performance lags far behind. The transmission ability of system interconnection becomes the bottleneck of embedded system performance improvement. Driven by technology and market, the International Standards Organization (ISO) and the International Electrotechnical Commission (IEC) introduced the international standard for embedded system interconnection, RapidIO (Rapid Input Output Interface). RapidIO Interconnection Specification for backplane, in October 2003. Due to the advantages of low power consumption and hardware cost, inter-chip communication is the best choice for embedded interconnection. FT-DSPx, a high-performance digital signal processor developed by Microelectronics Institute of National University of Science and Technology, is a multi-core processor. FT-DSPx integrates two serial RapidIO (SRIO) modules supporting the specification of RapidIO1.3 protocol for inter-chip interconnection and communication. The SRIO and DSP kernel are connected by the AMBA3.0AXI interface of ARM's on-chip bus protocol. In order to meet the needs of FT-DSPx interconnection, this paper designs a bridge component AMBA-SRIO bridge for the conversion of RapidIO protocol and AXI protocol. The main work of this paper includes: 1. In this paper, the specification of RapidIO1.3 protocol is studied systematically, and the architecture of RapidIO interconnection protocol is analyzed. The logical layer, transport layer and physical layer of RapidIO are studied and analyzed respectively. Based on the analysis of FT-DSPx system interconnection requirements, the overall design scheme of SRIO is presented. 2. Because SRIO and DSP kernel are connected by AMBA3.0AXI interface in DSP, a AMBA-SRIO bridge for AXI and RapidIO protocol conversion is designed based on the systematic study of AMBA3.0 bus protocol specification. The interface signal between the AMBA-SRIO bridge and the SRIO protocol layer module, including the input channel signal and the output channel signal, is given for reference to GRIO ULI Interface,. The interface signal between the AMBA-SRIO bridge and the AXI and the SRIO protocol layer signal are completed. 3. The function modules of AMBA-SRIO bridge, including control and status register configuration, address and transaction mapping logic, package unpacking module and asynchronous docking module, are designed and implemented in detail. The design of address and transaction mapping mechanism, package and unpack process and asynchronous docking using Graycode asynchronous FIFO are emphasized. 4. The AMBA-SRIO bridge designed in this paper is verified at the module level, component level and chip level. The verification of the chip level is emphasized, and the verification results are given and analyzed. The results show that the SRIO integrated with the AMBA-SRIO bridge can satisfy the I / O logic operation and doorbell transaction defined by the protocol specification, and can support the DMA operation. It is further verified that the AMBA-SRIO bridging component designed in this paper can meet the requirements of FT-DSPx interconnection. Finally, the result of logic synthesis is given. Based on the 65nm standard cell library of Synopsys Company, the area is 109.4051 渭 m ~ 2 and the power consumption is 10.1024 mwunder the condition of setting temperature 25 鈩
本文編號：2314393
[Abstract]:With the rapid development of VLSI, the performance of digital signal processor (DSP) has been improved, especially towards multi-core, but the increase of bus transmission performance lags far behind. The transmission ability of system interconnection becomes the bottleneck of embedded system performance improvement. Driven by technology and market, the International Standards Organization (ISO) and the International Electrotechnical Commission (IEC) introduced the international standard for embedded system interconnection, RapidIO (Rapid Input Output Interface). RapidIO Interconnection Specification for backplane, in October 2003. Due to the advantages of low power consumption and hardware cost, inter-chip communication is the best choice for embedded interconnection. FT-DSPx, a high-performance digital signal processor developed by Microelectronics Institute of National University of Science and Technology, is a multi-core processor. FT-DSPx integrates two serial RapidIO (SRIO) modules supporting the specification of RapidIO1.3 protocol for inter-chip interconnection and communication. The SRIO and DSP kernel are connected by the AMBA3.0AXI interface of ARM's on-chip bus protocol. In order to meet the needs of FT-DSPx interconnection, this paper designs a bridge component AMBA-SRIO bridge for the conversion of RapidIO protocol and AXI protocol. The main work of this paper includes: 1. In this paper, the specification of RapidIO1.3 protocol is studied systematically, and the architecture of RapidIO interconnection protocol is analyzed. The logical layer, transport layer and physical layer of RapidIO are studied and analyzed respectively. Based on the analysis of FT-DSPx system interconnection requirements, the overall design scheme of SRIO is presented. 2. Because SRIO and DSP kernel are connected by AMBA3.0AXI interface in DSP, a AMBA-SRIO bridge for AXI and RapidIO protocol conversion is designed based on the systematic study of AMBA3.0 bus protocol specification. The interface signal between the AMBA-SRIO bridge and the SRIO protocol layer module, including the input channel signal and the output channel signal, is given for reference to GRIO ULI Interface,. The interface signal between the AMBA-SRIO bridge and the AXI and the SRIO protocol layer signal are completed. 3. The function modules of AMBA-SRIO bridge, including control and status register configuration, address and transaction mapping logic, package unpacking module and asynchronous docking module, are designed and implemented in detail. The design of address and transaction mapping mechanism, package and unpack process and asynchronous docking using Graycode asynchronous FIFO are emphasized. 4. The AMBA-SRIO bridge designed in this paper is verified at the module level, component level and chip level. The verification of the chip level is emphasized, and the verification results are given and analyzed. The results show that the SRIO integrated with the AMBA-SRIO bridge can satisfy the I / O logic operation and doorbell transaction defined by the protocol specification, and can support the DMA operation. It is further verified that the AMBA-SRIO bridging component designed in this paper can meet the requirements of FT-DSPx interconnection. Finally, the result of logic synthesis is given. Based on the 65nm standard cell library of Synopsys Company, the area is 109.4051 渭 m ~ 2 and the power consumption is 10.1024 mwunder the condition of setting temperature 25 鈩
本文編號：2314393
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