【摘要】：隨著半導(dǎo)體工藝的發(fā)展,片上存儲(chǔ)器的設(shè)計(jì)容量和復(fù)雜度日益增長(zhǎng),傳統(tǒng)的功能驗(yàn)證方法面臨著驗(yàn)證完備性、可重用性、效率和可靠性等方面挑戰(zhàn).針對(duì)自主設(shè)計(jì)的某16路SIMD結(jié)構(gòu)的大容量向量存儲(chǔ)器(vector memory,VM)覆蓋率驅(qū)動(dòng)的驗(yàn)證方法進(jìn)行研究,基于SystemVerilog驗(yàn)證方法學(xué),采用層次化建模方法搭建了高效的VM驗(yàn)證平臺(tái),在較高抽象層次上實(shí)現(xiàn)了帶約束的隨機(jī)激勵(lì),結(jié)合SVA斷言技術(shù)對(duì)向量存儲(chǔ)器向量讀訪存流水線的同步與提交狀態(tài)實(shí)時(shí)監(jiān)控,保證了關(guān)鍵時(shí)序邏輯功能驗(yàn)證的完備性、正確性,有效提高了驗(yàn)證效率.最終模塊級(jí)驗(yàn)證結(jié)果表明,定向激勵(lì)和隨機(jī)激勵(lì)相結(jié)合能較快達(dá)到理想的代碼覆蓋率.
[Abstract]:With the development of semiconductor technology, the design capacity and complexity of on-chip memory are increasing day by day. Traditional functional verification methods face challenges of completeness, reusability, efficiency and reliability. In this paper, a self-designed verification method for a 16-channel SIMD structure with mass capacity vector memory (vector memory,VM) coverage driven is studied. Based on the SystemVerilog verification methodology, an efficient VM verification platform is built by using hierarchical modeling method. At a higher level of abstraction, the constrained random excitation is realized, and the synchronization and submission state of vector memory read and access pipeline is monitored in real time with SVA assertion technology, which ensures the completeness and correctness of the verification of key temporal logic functions. The efficiency of verification is improved effectively. The final modular level verification results show that the combination of directional excitation and random excitation can achieve an ideal code coverage quickly.
【作者單位】： 國(guó)防科學(xué)技術(shù)大學(xué)計(jì)算機(jī)學(xué)院;
【基金】：國(guó)家自然科學(xué)基金項(xiàng)目(61303065) 國(guó)防科學(xué)技術(shù)大學(xué)科研計(jì)劃基金項(xiàng)目(JC13-06-02) 教育部高等學(xué)校博士學(xué)科點(diǎn)專項(xiàng)科研基金項(xiàng)目(20134307120028)
【分類號(hào)】：TP333

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