【摘要】：為了使計(jì)算系統(tǒng)具有低功耗和容錯(cuò)能力,基于可逆邏輯設(shè)計(jì)了一種容錯(cuò)的通用移位寄存器。提出了一種新型的容錯(cuò)可逆邏輯門(Parity-preserving D flip_flop gate,PP_DFG),利用它和存在的容錯(cuò)門,完成了寄存器和多路數(shù)據(jù)選擇器的設(shè)計(jì)。綜合上述模塊,構(gòu)建了容錯(cuò)可逆的通用移位寄存器電路,用Verilog硬件描述語言建模,仿真顯示電路邏輯結(jié)構(gòu)正確。同現(xiàn)有電路相比,根據(jù)量子代價(jià)、延遲和無用輸出對(duì)其進(jìn)行性能評(píng)估,結(jié)果表明該電路不僅具有容錯(cuò)功能,而且性能提高了16%~48%。設(shè)計(jì)的電路可作為一種重要的存儲(chǔ)元件應(yīng)用于未來的低功耗計(jì)算系統(tǒng)。
[Abstract]:In order to make the computing system have low power consumption and fault-tolerant capability, a fault-tolerant general shift register is designed based on reversible logic. A novel fault-tolerant reversible logic gate (Parity-preserving D flip_flop gate,PP_DFG) is proposed. Using it and the existing fault-tolerant gate, the register and multiplexer are designed. A fault-tolerant and reversible universal shift register circuit is constructed by synthesizing the above modules. The Verilog hardware description language is used to model the model and the simulation results show that the logic structure of the circuit is correct. Compared with the existing circuit, the performance of the circuit is evaluated according to quantum cost, delay and useless output. The results show that the circuit not only has fault-tolerant function, but also improves its performance by 16 / 48. The designed circuit can be used as an important memory element in the future low-power computing system.
【作者單位】： 安徽師范大學(xué)數(shù)學(xué)計(jì)算機(jī)科學(xué)學(xué)院;安徽師范大學(xué)網(wǎng)絡(luò)與信息安全工程技術(shù)研究中心;
【基金】：國(guó)家自然科學(xué)基金項(xiàng)目(61370050) 安徽省自然科學(xué)基金項(xiàng)目(1308085QF118) 安徽省高校省級(jí)自然科學(xué)研究項(xiàng)目重點(diǎn)項(xiàng)目(KJ2014A084) 安徽師范大學(xué)創(chuàng)新基金項(xiàng)目(2013CXJJ01)資助
【分類號(hào)】：TP332.11

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