【摘要】：隨著社會(huì)的發(fā)展和信息量的增加，，人們對(duì)信息存儲(chǔ)系統(tǒng)速度和容量的需求不斷提升，對(duì)數(shù)據(jù)傳輸?shù)乃俣群涂煽啃砸蔡岢隽烁叩囊�。傳統(tǒng)的并行傳輸方式由于存在時(shí)鐘和數(shù)據(jù)間偏移，PCB布線難度大，信號(hào)間串?dāng)_嚴(yán)重等問題，已很難滿足高速系統(tǒng)的要求。而高速串行傳輸技術(shù)憑借其帶寬大、抗干擾性強(qiáng)和接口簡單等優(yōu)勢(shì)，正迅速取代傳統(tǒng)的并行技術(shù)，成為業(yè)界的主流。尤其是串行傳輸技術(shù)與現(xiàn)場可編程門陣列（FPGA）技術(shù)的結(jié)合，使得串行接口的設(shè)計(jì)變得更為簡單和靈活。 本文利用Xilinx公司Virtex-4系列FPGA中的串行接口模塊RocketIO MGT為主要數(shù)據(jù)傳輸手段，設(shè)計(jì)了一個(gè)高速視頻流存儲(chǔ)系統(tǒng)。該系統(tǒng)以Virtex-4系列FPGAXC4VFX100、ADSP BF537和NAND Flash K9NCG08U5M為核心器件，能夠?qū)Σ⑿蠰VDS接口、Fibre Channel4X光纖接口和Camera Link高速相機(jī)接口輸入的高速數(shù)據(jù)進(jìn)行實(shí)時(shí)的存儲(chǔ)，并能通過另一個(gè)Fibre Channel4X光纖接口對(duì)存儲(chǔ)數(shù)據(jù)進(jìn)行高速的下載，該系統(tǒng)同時(shí)還具有檢測(cè)壞塊的功能和規(guī)避壞塊的設(shè)計(jì)。此外，本文還對(duì)系統(tǒng)的關(guān)鍵部分進(jìn)行了必要的仿真，以驗(yàn)證設(shè)計(jì)的可行性。
[Abstract]:With the development of the society and the increase of the amount of information, the demand for the speed and capacity of the information storage system is increasing, and the speed and reliability of the data transmission are also required. Because of the clock and data offset, the difficulty of PCB routing and the serious crosstalk between signals, the traditional parallel transmission mode is difficult to meet the requirements of high-speed systems. The high-speed serial transmission technology, with its advantages of large bandwidth, strong anti-jamming and simple interface, is rapidly replacing the traditional parallel technology and becoming the mainstream of the industry. Especially the combination of serial transmission technology and field programmable gate array (FPGA) technology makes the design of serial interface more simple and flexible. In this paper, a high speed video stream storage system is designed by using the serial interface module RocketIO MGT in Virtex-4 series FPGA of Xilinx Company as the main means of data transmission. With Virtex-4 series FPGAXC4VFX100,ADSP BF537 and NAND Flash K9NCG08U5M as the core devices, the system can store the high speed data input from parallel LVDS interface, Fibre Channel4X fiber interface and Camera Link high speed camera interface in real time. It can download the stored data at high speed through another Fibre Channel4X fiber interface. The system also has the function of detecting bad blocks and avoiding the design of bad blocks. In addition, the key parts of the system are simulated to verify the feasibility of the design.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333

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本文編號(hào)：2287006