【摘要】：人們對(duì)處理器不斷增長(zhǎng)的應(yīng)用需求促進(jìn)處理器體系結(jié)構(gòu)的不斷發(fā)展，也促使新型處理器體系結(jié)構(gòu)的誕生。多核流處理器是針對(duì)流式數(shù)據(jù)處理和流應(yīng)用的新型多核處理器，以數(shù)量眾多的簡(jiǎn)單核構(gòu)成。其對(duì)于計(jì)算密集型應(yīng)用，數(shù)據(jù)吞吐率大，，資源利用率高，但是對(duì)于訪存密集型和稀疏類應(yīng)用性能較差。傳統(tǒng)多核結(jié)構(gòu)適用于訪存密集型和稀疏類應(yīng)用，然而對(duì)于流應(yīng)用，其Cache結(jié)構(gòu)不能高效捕獲流應(yīng)用的數(shù)據(jù)局部性。為了滿足流應(yīng)用與傳統(tǒng)多核應(yīng)用的綜合需求，為了實(shí)現(xiàn)多核流處理器與傳統(tǒng)多核處理器的融合，我們提出了同構(gòu)通用流多核處理器體系結(jié)構(gòu)：片內(nèi)集成多個(gè)同構(gòu)的流多核，流多核可根據(jù)具體應(yīng)用配置為傳統(tǒng)多核或流多核的一部分。傳統(tǒng)多核與流多核主要的區(qū)別在于訪存部件，前者是以Cache結(jié)構(gòu)為主的片上緩存結(jié)構(gòu)，后者則是由寄存器文件和片上便簽存儲(chǔ)器構(gòu)成。通過(guò)配置流多核內(nèi)部的共享的片上存儲(chǔ)資源，調(diào)節(jié)便簽存儲(chǔ)器和Cache結(jié)構(gòu)所占的比例，實(shí)現(xiàn)同構(gòu)通用流多核處理器對(duì)多種應(yīng)用需求的適用性。其中Cache結(jié)構(gòu)針對(duì)傳統(tǒng)多核的應(yīng)用，解決其數(shù)據(jù)上的時(shí)間和空間局部性，便簽存儲(chǔ)器主要捕捉流應(yīng)用中數(shù)據(jù)的生產(chǎn)者-消費(fèi)者局部性。 本課題對(duì)流多核體系結(jié)構(gòu)訪存部件關(guān)鍵技術(shù)進(jìn)行了深入研究，主要工作和創(chuàng)新點(diǎn)包括： 1、提出了一種可配置的片上共享SPM/L2Cache結(jié)構(gòu)。同構(gòu)通用流處理器的應(yīng)用范圍包括傳統(tǒng)應(yīng)用和流應(yīng)用，其基本組成單元流多核面向不同應(yīng)用時(shí)可分別按片上SMP執(zhí)行模式和SIMT執(zhí)行模式運(yùn)行。在不同的運(yùn)行模式下對(duì)片上共享存儲(chǔ)結(jié)構(gòu)進(jìn)行合理配置，以滿足處理器對(duì)存儲(chǔ)部件的需求。 2、設(shè)計(jì)了針對(duì)流多核片上緩存結(jié)構(gòu)特點(diǎn)的數(shù)據(jù)一致性維護(hù)協(xié)議。流多核一級(jí)私有Cache是寫穿透策略，二級(jí)共享Cache的寫策略是寫回，在此基礎(chǔ)上，通過(guò)作廢被修改的Cacheline的拷貝來(lái)維護(hù)兩級(jí)緩存之間數(shù)據(jù)一致性。 3、設(shè)計(jì)了流核心私有的一級(jí)數(shù)據(jù)緩存。在Microblaze軟核Cache模塊的基礎(chǔ)上，通過(guò)數(shù)據(jù)寬度64位擴(kuò)展和增加支持一致性維護(hù)的邏輯電路，完成了流多核架構(gòu)中的最內(nèi)層緩存結(jié)構(gòu)的設(shè)計(jì)。 4、基于Xilinx公司的軟件開發(fā)平臺(tái)下，對(duì)流多核存儲(chǔ)部件的關(guān)鍵邏輯設(shè)計(jì)進(jìn)行了行為仿真，并進(jìn)行了一定的性能分析。驗(yàn)證結(jié)果顯示所有設(shè)計(jì)均實(shí)現(xiàn)了預(yù)定的功能，同時(shí)性能分析顯示了本文設(shè)計(jì)的有效性。
[Abstract]:The increasing demand for processor applications promotes the development of processor architecture and the birth of new processor architecture. Multi-core stream processor is a new type of multi-core processor for streaming data processing and streaming applications, which consists of a large number of simple cores. It has high data throughput and high resource utilization for computationally intensive applications, but it has poor performance for memory access intensive and sparse applications. Traditional multicore architecture is suitable for memory access intensive and sparse class applications. However, for stream applications, the Cache structure can not capture the data localization of stream applications efficiently. In order to meet the integrated requirements of streaming applications and traditional multi-core applications, and to integrate multi-core stream processors with traditional multi-core processors, we propose an isomorphic universal stream multi-core processor architecture, in which multiple isomorphic streams and multi-cores are integrated on a chip. Stream multicore can be configured as part of traditional multicore or stream multicore according to specific application. The main difference between traditional multi-core and streaming multi-core is memory access. The former is based on Cache structure and the latter is composed of register file and on-chip note memory. By configuring the shared on-chip storage resources within the stream multi-core and adjusting the proportion of the note memory and the Cache structure, the applicability of the isomorphic universal stream multi-core processor to various application requirements is realized. The Cache structure solves the temporal and spatial localization of the data for the traditional multi-core applications, and the note memory mainly captures the producer-consumer locality of the data in the stream application. In this paper, the key technologies of memory access components in convection multicore architecture are deeply studied. The main work and innovations are as follows: 1. A configurable shared SPM/L2Cache architecture is proposed. The application scope of isomorphic general flow processor includes traditional application and stream application. Its basic component, cell stream multi-core, can be run according to on-chip SMP execution mode and SIMT execution mode respectively when it is oriented to different applications. In order to meet the memory requirements of the processor, a data consistency maintenance protocol is designed for the characteristics of streaming multi-core on-chip buffer structure. Stream multi-core primary private Cache is write penetration strategy, secondary shared Cache write strategy is write back, on this basis, The data consistency between the two levels of cache is maintained by canceling the modified copy of Cacheline. 3. The primary data cache which is private to the stream core is designed. On the basis of Microblaze soft core Cache module, through the data width of 64-bit expansion and add support for consistency maintenance of the logic circuit, The design of the innermost buffer structure in the stream multi-core architecture is completed. 4. Based on the software development platform of Xilinx, the behavior simulation of the key logic design of the convection multi-core storage unit is carried out, and the performance analysis is given. The verification results show that all the designs achieve the intended function, and the performance analysis shows the effectiveness of the design.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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