【摘要】：在多核處理器和流處理器的發(fā)展都受到限制時，CPU和GPU的異構(gòu)結(jié)構(gòu)在超級計算機領(lǐng)域創(chuàng)造了性能神話�？墒钱悩�(gòu)體系結(jié)構(gòu)在功耗和數(shù)據(jù)存儲上存在先天性不足，成為其性能瓶頸。因此，CPU和GPU的同構(gòu)系統(tǒng)漸漸受到業(yè)界重視，即同構(gòu)通用流處理器。 同構(gòu)通用流處理器是發(fā)揮CPU控制能力和GPU數(shù)據(jù)處理能力的融合產(chǎn)品，其流核心應(yīng)在滿足強大計算性能的同時具有一定的控制能力和可編程能力。根據(jù)這一原則，本文基于Microblaze的RISC指令集設(shè)計64位流水線并進行優(yōu)化。為滿足同構(gòu)通用流處理器的性能要求，，所做的工作包括： 1.基于Microblaze的32位指令集，設(shè)計64位流水線，對數(shù)據(jù)結(jié)構(gòu)進行64位擴展，以適應(yīng)流處理器的運算精度要求以及尋址空間的擴展需要； 2.在細(xì)致分析分支指令執(zhí)行特征的基礎(chǔ)上，對流水線添加基于歷史信息的分支預(yù)測功能，以改善循環(huán)和嵌套執(zhí)行的條件跳轉(zhuǎn)類分支指令的執(zhí)行效率。另外，分支預(yù)測功能可基本消除無條件跳轉(zhuǎn)類分支的執(zhí)行開銷； 3.修改流水線控制信號，在浮點部件中添加流水控制邏輯，讓除浮點除和浮點開方指令的其余浮點指令可以流水化執(zhí)行。浮點流水的設(shè)計原則是指令的順序執(zhí)行。 論文在Xilinx公司的仿真軟件Isim上對流水線進行了全面的功能驗證，綜合資源利用率情況對其進行性能比較。測試激勵本著窮盡原則編寫。仿真結(jié)果顯示設(shè)計實現(xiàn)了預(yù)期的功能要求。
[Abstract]:At a time when the development of multi-core processors and stream processors is limited, the heterogeneous structures of CPU and GPU create a performance myth in the field of supercomputers. However, there are inherent deficiencies in power consumption and data storage in heterogeneous architecture, which is the bottleneck of its performance. Therefore, the isomorphism system of CPU and GPU has been paid more and more attention, that is, isomorphic universal stream processor. The isomorphic general stream processor is a fusion product which exerts the CPU control ability and the GPU data processing ability. Its stream core should have certain control ability and programmable ability while satisfying the powerful computing performance. According to this principle, this paper designs and optimizes 64 bit pipeline based on RISC instruction set of Microblaze. In order to meet the performance requirements of the isomorphic universal stream processor, the work done includes: 1. Based on 32-bit instruction set of Microblaze, 64-bit pipeline is designed to extend the data structure in order to meet the demand of computational precision and addressable space expansion of flow processor. 2. Based on the detailed analysis of the execution characteristics of branch instructions, a branch prediction function based on historical information is added to the pipeline to improve the execution efficiency of conditional jump branch instructions for loop and nested execution. In addition, the branch prediction function can basically eliminate the execution overhead of the unconditional jump class branch; 3. The pipeline control signal is modified and the pipeline control logic is added to the floating-point component so that the other floating-point instructions except the floating-point except for floating-point and floating-point opening instructions can be pipelined. The design principle of floating-point pipelining is the sequential execution of instructions. In this paper, the function of pipeline is verified on the simulation software Isim of Xilinx Company, and the performance of pipeline is compared by comprehensive resource utilization. Test incentives are written on an exhaustive basis. Simulation results show that the design achieves the expected functional requirements.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332

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相關(guān)期刊論文 前2條

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