發(fā)布時間：2018-10-15 15:19

【摘要】：隨著集成電路工藝的進步以及計算機技術(shù)的不斷發(fā)展,片上多核處理器正逐步取代傳統(tǒng)的單核處理器成為未來的主流。然而由于芯片集成度的提高,芯片的功耗密度也越來越大,功耗問題已經(jīng)成為制約高性能處理器進一步發(fā)展的瓶頸。而cache作為連接cpu以及主存之間的緩沖區(qū),其在系統(tǒng)的數(shù)據(jù)傳輸及存儲中發(fā)揮著重要作用。而且由于cache面積的不斷增加,其在片上多核系統(tǒng)中所占的功耗比例也越來越大。因此降低cache的功耗對于優(yōu)化整個片上多核系統(tǒng)的功耗有著至關(guān)重要的作用。本文從程序的訪存特性入手來優(yōu)化片上緩存的功耗問題。在程序運行的過程中,通過統(tǒng)計發(fā)現(xiàn)可以將緩存的訪問分為協(xié)議訪問和數(shù)據(jù)訪問兩種類型,而且其中協(xié)議訪問占據(jù)了幾乎一半的訪問空間。因此,我們提出了一種軟硬件協(xié)同的緩存功耗管控方案。該方案是基于現(xiàn)有管控方案中電壓門控技術(shù)和緩存衰退機制之上改進的一種管控方案,該方案可以在滿足程序性能約束的前提下,極大程度上降低系統(tǒng)的功耗。另一方面,在程序運行的過程中,通過跟蹤線程的訪存行為發(fā)現(xiàn)有些線程私有的數(shù)據(jù)被映射到了離線程較遠的地址空間上。該訪問特性導(dǎo)致了訪問延時的增加以及網(wǎng)絡(luò)擁塞所引起的網(wǎng)絡(luò)功耗的增加。因此本文提出了一種線程私有數(shù)據(jù)地址空間重映射的算法,在一定程度上實現(xiàn)了系統(tǒng)的性能及功耗的雙重優(yōu)化。最后,為了驗證本文功耗管控方案的有效性,本文通過軟件仿真器對該方案進行了仿真驗證,同時也和現(xiàn)有的其他方案進行了對比。仿真結(jié)果表明,本文提出的方案可以在對系統(tǒng)造成低于3%的性能損失條件下,降低系統(tǒng)平均75%的功耗。此外,對多線程技術(shù)的優(yōu)化運用到該方案上可以進一步降低系統(tǒng)約3%的網(wǎng)絡(luò)功耗以及1%的性能損失。
[Abstract]:With the progress of integrated circuit technology and the development of computer technology, the multi-core processor on chip is gradually replacing the traditional single-core processor as the mainstream of the future. However, due to the increase of chip integration, the power density of the chip is also increasing, power consumption has become a bottleneck restricting the further development of high-performance processors. As a buffer between cpu and main memory, cache plays an important role in data transmission and storage. Moreover, with the increasing of cache area, the power consumption of cache in the on-chip multicore system is increasing. Therefore, reducing the power consumption of cache plays an important role in optimizing the power consumption of the whole on-chip multi-core system. In this paper, the memory access characteristics of the program to optimize the power consumption of on-chip cache. In the process of program running, the cached access can be divided into two types: protocol access and data access, and protocol access occupies almost half of the access space. Therefore, we propose a cache power management scheme based on hardware and software co-operation. This scheme is an improved control scheme based on the voltage gating technology and the buffer degradation mechanism in the existing control schemes. The scheme can greatly reduce the power consumption of the system on the premise of satisfying the program performance constraints. On the other hand, in the process of running the program, it is found that some thread-private data are mapped to the address space far away from the thread by tracking the memory access behavior of the thread. This access characteristic leads to the increase of access delay and the increase of network power consumption caused by network congestion. Therefore, this paper proposes an algorithm of thread private data address space remapping, which can optimize the performance and power consumption of the system to a certain extent. Finally, in order to verify the effectiveness of the proposed power management scheme, this paper simulates the scheme by software simulator, and compares it with other existing schemes. The simulation results show that the proposed scheme can reduce the average power consumption of the system by 75% under the condition that the performance loss is less than 3%. In addition, the application of multi-thread technology to the scheme can further reduce the network power consumption of the system by about 3% and the performance loss of 1%.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TP332

【參考文獻】

相關(guān)期刊論文 前1條

1 陳天洲,黃江偉,戴鴻君;The dynamic power management for embedded system with Poisson process[J];Journal of Zhejiang University Science A(Science in Engineering);2005年S1期

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本文編號：2272950