【摘要】：針對(duì)高密度存儲(chǔ)服務(wù)器中高速鏈路結(jié)構(gòu)復(fù)雜、信號(hào)速率高、鏈路長(zhǎng)度長(zhǎng)等特點(diǎn),在高速鏈路PCIE3.0和SAS3.0設(shè)計(jì)過程中引入全面的信號(hào)完整性仿真。通過對(duì)高速印刷電路板設(shè)計(jì)中拓?fù)浣Y(jié)構(gòu)、材料類型、印刷電路板結(jié)構(gòu)等關(guān)鍵項(xiàng)目進(jìn)行仿真設(shè)計(jì),獲得成本最低、性能達(dá)標(biāo)的最優(yōu)方案;通過全鏈路有源仿真,預(yù)估系統(tǒng)性能,降低系統(tǒng)投產(chǎn)風(fēng)險(xiǎn);通過系統(tǒng)實(shí)際信號(hào)測(cè)試,驗(yàn)證系統(tǒng)性能完全滿足相應(yīng)規(guī)范要求,仿真結(jié)果有效可靠。
[Abstract]:In view of the characteristics of high speed link structure, high signal rate and long link length in high density storage server, comprehensive signal integrity simulation is introduced into the design process of high speed link PCIE3.0 and SAS3.0. By simulating the key items in the design of high speed printed circuit board, such as topology structure, material type, printed circuit board structure and so on, the optimal scheme with the lowest cost and up to standard performance is obtained, and the system performance is estimated by the full link active simulation. It can reduce the risk of system putting into production and verify that the performance of the system can meet the requirements of the corresponding specification and the simulation result is effective and reliable through the testing of the actual signal of the system.
【作者單位】： 北京科技大學(xué)計(jì)算機(jī)與通信工程學(xué)院;曙光信息產(chǎn)業(yè)有限公司;哈爾濱工程大學(xué)水聲工程學(xué)院;中國(guó)科學(xué)院微電子研究所;
【基金】：國(guó)家“863”高技術(shù)研究發(fā)展計(jì)劃基金資助項(xiàng)目(2013AA01A209) 北京市科委計(jì)劃項(xiàng)目(D141100003414002)
【分類號(hào)】：TP333

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