【摘要】：針對高密度存儲服務器中高速鏈路結(jié)構(gòu)復雜、信號速率高、鏈路長度長等特點,在高速鏈路PCIE3.0和SAS3.0設計過程中引入全面的信號完整性仿真。通過對高速印刷電路板設計中拓撲結(jié)構(gòu)、材料類型、印刷電路板結(jié)構(gòu)等關(guān)鍵項目進行仿真設計,獲得成本最低、性能達標的最優(yōu)方案;通過全鏈路有源仿真,預估系統(tǒng)性能,降低系統(tǒng)投產(chǎn)風險;通過系統(tǒng)實際信號測試,驗證系統(tǒng)性能完全滿足相應規(guī)范要求,仿真結(jié)果有效可靠。
[Abstract]:In view of the characteristics of high speed link structure, high signal rate and long link length in high density storage server, comprehensive signal integrity simulation is introduced into the design process of high speed link PCIE3.0 and SAS3.0. By simulating the key items in the design of high speed printed circuit board, such as topology structure, material type, printed circuit board structure and so on, the optimal scheme with the lowest cost and up to standard performance is obtained, and the system performance is estimated by the full link active simulation. It can reduce the risk of system putting into production and verify that the performance of the system can meet the requirements of the corresponding specification and the simulation result is effective and reliable through the testing of the actual signal of the system.
【作者單位】： 北京科技大學計算機與通信工程學院;曙光信息產(chǎn)業(yè)有限公司;哈爾濱工程大學水聲工程學院;中國科學院微電子研究所;
【基金】：國家“863”高技術(shù)研究發(fā)展計劃基金資助項目(2013AA01A209) 北京市科委計劃項目(D141100003414002)
【分類號】：TP333

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