一款高性能處理器的可測(cè)性設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2018-10-10 09:50
【摘要】：隨著深亞微米(DSM, Deep Sub-Micron)技術(shù)和IP (Intellectual Property)核復(fù)用技術(shù)為支撐的片上系統(tǒng)SoC (System-on-Chip)技術(shù)的迅速發(fā)展,高性能處理器的可測(cè)試性設(shè)計(jì)(DFT, Design For Testability)已經(jīng)成為了設(shè)計(jì)過(guò)程中的重要一環(huán),成為了一項(xiàng)極具挑戰(zhàn)性的工作。 本課題主要是實(shí)現(xiàn)了一款高性能處理器的DFT設(shè)計(jì),該芯片采用45nm設(shè)計(jì)工藝,主頻1.2GHz。芯片不僅自身邏輯模塊結(jié)構(gòu)復(fù)雜,而且使用了DDR3、 PCIE、 SATA、USB等高速I(mǎi)P核,這就給處理器的可測(cè)試性設(shè)計(jì)帶來(lái)了更大的挑戰(zhàn)。為達(dá)到芯片的測(cè)試目標(biāo)和提高芯片的易測(cè)性,我們采取的DFT方法主要包括：掃描設(shè)計(jì)、存儲(chǔ)器內(nèi)建自測(cè)試、邊界掃描設(shè)計(jì),這些技術(shù)為該芯片提供了方便可靠的測(cè)試方案。 在簡(jiǎn)單論述了可測(cè)性設(shè)計(jì)的基本理論、方法和芯片的整體結(jié)構(gòu)后,本文主要闡述了處理器可測(cè)性設(shè)計(jì)的實(shí)現(xiàn),并且針對(duì)實(shí)現(xiàn)過(guò)程中的一些難點(diǎn)和重點(diǎn)做了詳細(xì)的闡述,本文的主要工作和創(chuàng)新點(diǎn)總結(jié)如下： 1、在at-speed測(cè)試方案下,結(jié)合DFT方法,通過(guò)解決時(shí)鐘域、門(mén)控時(shí)鐘以及壓縮邏輯等復(fù)雜問(wèn)題,使芯片Transition故障覆蓋率達(dá)到了90%左右,Stuck-at故障覆蓋率達(dá)到了96.31%,達(dá)到了預(yù)期的測(cè)試要求。 2、掃描設(shè)計(jì)通過(guò)“低功耗填充”技術(shù),有效的生成低功耗的測(cè)試向量,該技術(shù)將測(cè)試向量的每個(gè)關(guān)注位的值復(fù)制到掃描鏈中的后續(xù)位,直到下一個(gè)具有相反值關(guān)注位出現(xiàn)為止,產(chǎn)生低功耗的測(cè)試向量,該設(shè)計(jì)方法使單個(gè)模塊的掃描功耗比正常情況下平均降低了22.46%。 3、由于芯片內(nèi)的存儲(chǔ)器數(shù)目繁多,如果用一般的設(shè)計(jì)方法,MBIST的測(cè)試功耗將非常高。而本文采取了一種降低MBIST功耗的設(shè)計(jì)方法,該方法根據(jù)時(shí)鐘域、存儲(chǔ)器大小將存儲(chǔ)器分成不同的組,組之間進(jìn)行串行測(cè)試,組內(nèi)并行測(cè)試,該方法使得測(cè)試功耗與傳統(tǒng)的測(cè)試功耗相比降低了14.36%。 目前該芯片的DFT設(shè)計(jì)工作已經(jīng)全部結(jié)束,芯片正處于流片階段,整個(gè)芯片的DFT結(jié)構(gòu)已經(jīng)全部通過(guò)模擬驗(yàn)證,證明整個(gè)設(shè)計(jì)符合測(cè)試要求。
[Abstract]:With the rapid development of deep submicron (DSM, Deep Sub-Micron technology and SoC (System-on-Chip) technology supported by IP (Intellectual Property) core reuse technology, the testability design (DFT, Design For Testability) of high performance processors has become an important part of the design process. Has become a very challenging job. The main task of this paper is to implement the DFT design of a high performance processor. The chip adopts 45nm design technology and the main frequency is 1.2 GHz. The chip not only has complex logic module structure, but also uses high speed IP core such as DDR3, PCIE, SATA,USB, which brings more challenges to the testability design of the processor. In order to achieve the test goal of the chip and improve the testability of the chip, the DFT methods we adopt mainly include: scan design, memory built-in self-test, and boundary scan design. These technologies provide a convenient and reliable test scheme for the chip. After briefly discussing the basic theory, method and the whole structure of the chip, this paper mainly describes the realization of the testability design of the processor, and gives a detailed description of some difficulties and emphases in the process of implementation. The main work and innovations of this paper are summarized as follows: 1. Under the at-speed test scheme, combining with the DFT method, the complex problems such as clock domain, gated clock and compression logic are solved. The fault coverage of chip Transition reaches about 90% and the coverage rate of Stuck-at reaches 96.31, which meets the expected test requirements. 2. The scan design effectively generates low-power test vectors through "low-power fill" technology, which copies the value of each concern bit of the test vector to a subsequent bit in the scan chain until the next one with the opposite value of concern appears. A low power test vector is generated, and the scanning power consumption of a single module is reduced by 22.46 than normal. 3. Because of the large number of memory in the chip, the test power consumption of MBIST will be very high if the general design method is used. In this paper, we adopt a design method to reduce the power consumption of MBIST. According to the clock domain and memory size, the memory is divided into different groups. This method reduces the test power consumption by 14.36 compared with the traditional test power. At present, the DFT design of the chip has been completed, the chip is in the flow stage, and the DFT structure of the whole chip has been verified by simulation, which proves that the whole design meets the test requirements.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332;TN47
本文編號(hào)：2261317
[Abstract]:With the rapid development of deep submicron (DSM, Deep Sub-Micron technology and SoC (System-on-Chip) technology supported by IP (Intellectual Property) core reuse technology, the testability design (DFT, Design For Testability) of high performance processors has become an important part of the design process. Has become a very challenging job. The main task of this paper is to implement the DFT design of a high performance processor. The chip adopts 45nm design technology and the main frequency is 1.2 GHz. The chip not only has complex logic module structure, but also uses high speed IP core such as DDR3, PCIE, SATA,USB, which brings more challenges to the testability design of the processor. In order to achieve the test goal of the chip and improve the testability of the chip, the DFT methods we adopt mainly include: scan design, memory built-in self-test, and boundary scan design. These technologies provide a convenient and reliable test scheme for the chip. After briefly discussing the basic theory, method and the whole structure of the chip, this paper mainly describes the realization of the testability design of the processor, and gives a detailed description of some difficulties and emphases in the process of implementation. The main work and innovations of this paper are summarized as follows: 1. Under the at-speed test scheme, combining with the DFT method, the complex problems such as clock domain, gated clock and compression logic are solved. The fault coverage of chip Transition reaches about 90% and the coverage rate of Stuck-at reaches 96.31, which meets the expected test requirements. 2. The scan design effectively generates low-power test vectors through "low-power fill" technology, which copies the value of each concern bit of the test vector to a subsequent bit in the scan chain until the next one with the opposite value of concern appears. A low power test vector is generated, and the scanning power consumption of a single module is reduced by 22.46 than normal. 3. Because of the large number of memory in the chip, the test power consumption of MBIST will be very high if the general design method is used. In this paper, we adopt a design method to reduce the power consumption of MBIST. According to the clock domain and memory size, the memory is divided into different groups. This method reduces the test power consumption by 14.36 compared with the traditional test power. At present, the DFT design of the chip has been completed, the chip is in the flow stage, and the DFT structure of the whole chip has been verified by simulation, which proves that the whole design meets the test requirements.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332;TN47
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 蔣敬旗,周旭,李文,范東睿;系統(tǒng)芯片中低功耗測(cè)試的幾種方法[J];微電子學(xué)與計(jì)算機(jī);2002年10期
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