M-DSP定點運算單元及混洗單元的設計驗證與優(yōu)化
發(fā)布時間：2018-10-09 21:48
【摘要】：隨著航空航天、通信、醫(yī)療等領域中數(shù)據(jù)處理量的增大以及實時信息處理能力的需求提升,使得高性能DSP(Digital Signal Processing)成為國內(nèi)外的研究熱點。M-DSP是一款自主研發(fā)的32位高性能DSP,采用11發(fā)射的超長指令字(VLIW)體系結構,擁有強大的并行計算能力,在40nm工藝下主頻達1GHz。本文基于M-DSP的研發(fā)平臺,完成IALU單元和混洗單元的設計、優(yōu)化、驗證工作,主要內(nèi)容如下:一、根據(jù)M-DSP的設計需求,設計了IALU單元的指令集和微體系結構,并實現(xiàn)了兩種各具優(yōu)點的IALU單元設計方案。一種是以Kogge-Stone樹為核心的加法器分立式IALU結構,具有較好的時序,而且便于采用門控精細控制功耗,但面積較大;另一種是二級超前進位加法器IALU結構,IALU大多數(shù)指令通過復用加法器實現(xiàn),IALU單元面積較小,但其結構復雜,時序相對較差。本文根據(jù)M-DSP的設計需要最終采用第一種實現(xiàn)方案。二、目前,傳統(tǒng)的混洗指令需要使用Load指令提前加載混洗模式,這種方式占用過多的系統(tǒng)寄存器資源并且執(zhí)行周期較長。為克服上述問題,本文設計了一款配置和執(zhí)行相分離,并且擁有特定的混洗模式地址寄存器和混洗模式存儲體的高效混洗單元。三、針對本文所設計的IALU單元和混洗單元的特點,設計了完整詳細的驗證方案。主要采用模擬驗證的方法,分別從模塊級到系統(tǒng)級對IALU單元和混洗單元進行驗證。模塊級驗證包括功能點、ATEC和隨機數(shù)驗證;系統(tǒng)級包括全局信號和指令組合驗證等,并對驗證情況做覆蓋率統(tǒng)計,分析消除驗證盲點。另外,采用形式化驗證的方法,驗證綜合后網(wǎng)表和RTL級代碼的一致性。四、分別對IALU單元和混洗單元設計采用樹狀選擇結構、邏輯優(yōu)化和流水線技術等方法進行時序優(yōu)化,并采用門控時鐘、邏輯重組、操作數(shù)隔離和狀態(tài)碼優(yōu)化等方法進行RTL級功耗優(yōu)化。最后在40nm CMOS工藝下,使用Design Complier綜合工具對IALU單元和Shuffle單元進行綜合,其中IALU關鍵路徑延時為400ps,總面積為7004.2372um2;Shuffle單元關鍵路徑延時為430ps,總面積為151811.721um2,結果表明其性能、面積達到M-DSP的設計要求。
[Abstract]:With the increase of data processing capacity in aerospace, communication, medical and other fields, as well as the need for real-time information processing capacity, High performance DSP (Digital Signal Processing) has become a research hotspot at home and abroad. M-DSP is a self-developed 32-bit high performance DSP, (VLIW) architecture with 11-transmitted super-long instruction word. It has powerful parallel computing capability and the main frequency reaches 1 GHz in the 40nm process. Based on the research and development platform of M-DSP, this paper completes the design, optimization and verification of IALU unit and washing unit. The main contents are as follows: 1. According to the design requirements of M-DSP, the instruction set and microarchitecture of IALU unit are designed. Two IALU element design schemes with each advantage are implemented. One is a discrete IALU structure with Kogge-Stone tree as the core, which has better timing, and is convenient to use gated fine control power consumption, but the area is large. The other is that the IALU structure of the two-stage carry-ahead adder is small in area, but its structure is complex and the timing is relatively poor. According to the design needs of M-DSP, the first implementation scheme is adopted in this paper. Second at present the traditional shuffling instruction needs to load the washing mode in advance with Load instruction which takes up too much system register resource and has a long execution period. In order to overcome the above problems, this paper designs an efficient shuffling unit with a separate configuration and execution phase, and has a specific address register of the shuffling mode and the memory of the shuffling mode. Thirdly, according to the characteristics of the IALU unit and the washing unit designed in this paper, a complete and detailed verification scheme is designed. The IALU unit and the washing unit are verified from module level to system level by the method of simulation verification. Module level verification includes function point ATEC and random number verification, and system level includes global signal and instruction combination verification. In addition, the method of formal verification is used to verify the consistency between the net table and the RTL level code. Fourthly, the IALU unit and the washing unit are designed using tree selection structure, logic optimization and pipeline technology, respectively, and the timing is optimized by gating clock, logic recombination, etc. Operand isolation and state code optimization are used to optimize power consumption at RTL level. Finally, the Design Complier synthesis tool is used to synthesize the IALU unit and the Shuffle unit in 40nm CMOS process. The critical path delay of IALU is 400ps. the total area is 7004.2372um2Shuffle, the critical path delay is 430psand the total area is 151811.721um2. The result shows its performance. The area meets the design requirements of M-DSP.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP332
本文編號：2260906
[Abstract]:With the increase of data processing capacity in aerospace, communication, medical and other fields, as well as the need for real-time information processing capacity, High performance DSP (Digital Signal Processing) has become a research hotspot at home and abroad. M-DSP is a self-developed 32-bit high performance DSP, (VLIW) architecture with 11-transmitted super-long instruction word. It has powerful parallel computing capability and the main frequency reaches 1 GHz in the 40nm process. Based on the research and development platform of M-DSP, this paper completes the design, optimization and verification of IALU unit and washing unit. The main contents are as follows: 1. According to the design requirements of M-DSP, the instruction set and microarchitecture of IALU unit are designed. Two IALU element design schemes with each advantage are implemented. One is a discrete IALU structure with Kogge-Stone tree as the core, which has better timing, and is convenient to use gated fine control power consumption, but the area is large. The other is that the IALU structure of the two-stage carry-ahead adder is small in area, but its structure is complex and the timing is relatively poor. According to the design needs of M-DSP, the first implementation scheme is adopted in this paper. Second at present the traditional shuffling instruction needs to load the washing mode in advance with Load instruction which takes up too much system register resource and has a long execution period. In order to overcome the above problems, this paper designs an efficient shuffling unit with a separate configuration and execution phase, and has a specific address register of the shuffling mode and the memory of the shuffling mode. Thirdly, according to the characteristics of the IALU unit and the washing unit designed in this paper, a complete and detailed verification scheme is designed. The IALU unit and the washing unit are verified from module level to system level by the method of simulation verification. Module level verification includes function point ATEC and random number verification, and system level includes global signal and instruction combination verification. In addition, the method of formal verification is used to verify the consistency between the net table and the RTL level code. Fourthly, the IALU unit and the washing unit are designed using tree selection structure, logic optimization and pipeline technology, respectively, and the timing is optimized by gating clock, logic recombination, etc. Operand isolation and state code optimization are used to optimize power consumption at RTL level. Finally, the Design Complier synthesis tool is used to synthesize the IALU unit and the Shuffle unit in 40nm CMOS process. The critical path delay of IALU is 400ps. the total area is 7004.2372um2Shuffle, the critical path delay is 430psand the total area is 151811.721um2. The result shows its performance. The area meets the design requirements of M-DSP.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP332
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