基于嵌入式多核平臺可視化性能監(jiān)視系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)
[Abstract]:With the rapid development of information technology, embedded technology has made unprecedented progress. At present, embedded systems have been widely used in life, military, aerospace and other fields, which put forward higher requirements for the stability and computing speed of embedded systems. The single-core system can not meet the increasing demand for embedded computing power, so multi-core parallel system becomes an effective solution to improve the embedded processing capacity. The four-core S698P4 development board based on SPARC architecture produced by Zhuhai Orbita Company is a parallel multi-core embedded system using SMP technology. It is widely used in high reliability embedded fields such as aviation and aerospace. Because of the large area application of embedded system, the demand of embedded program development is more and more urgent. With the emergence of many embedded real-time operating systems, the threshold of embedded program development is greatly reduced. As a small, configurable real-time embedded operating system, the ECos system has been widely used in the embedded field. However, there are still some problems in embedded program development, such as shortage of hardware resources, low efficiency of program operation, etc. Especially for multi-core embedded systems, how to allocate resources equally, so that all kinds of resources can be fully and effectively utilized. It is still a difficult problem in embedded program development. Aiming at the problem that multi-core embedded program development can not directly understand the use of hardware resources, a visual performance monitoring system based on embedded multi-core platform is developed in this paper. This system can not only display the utilization rate of CPU kernel and memory in real time, but also analyze the bottleneck of software and hardware based on these data, and enumerate the shortcomings of program design. The system can also capture a variety of common operations on the memory in the program, analyze the common hidden trouble and error of the memory operation in the program, make the program more reasonable and reliable. At the end of this paper, the system is tested on line, and some typical example programs are selected to test the module and test synthetically, and the results of running are analyzed and compared in detail. The correctness and reliability of the data monitored by the system are verified. Finally, some work done in this paper is analyzed and summarized, the value and significance of the program are explained, and the future work is prospected.
【學(xué)位授予單位】:哈爾濱工業(yè)大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2013
【分類號】:TP368.1;TP316.2
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