【摘要】：YHFT-Matrix是國防科大研發(fā)的具有自主知識產(chǎn)權的面向無線通信、視頻和圖像處理的高性能浮點DSP(Digital Signal Processor)軟核。為解決DSP的數(shù)據(jù)供給問題,本文設計了一個功能強大的搬移數(shù)據(jù)的部件——直接存儲器訪問控制器(Direct Memory Access Controller,DMAC)。本文主要工作和成果包括:1.深入分析該DSP的體系結(jié)構(gòu)和應用需求,完成了一個多通道多總線的DMA控制器的整體結(jié)構(gòu)設計,并對DMA控制器的地址作了參數(shù)化設計。2.為滿足核內(nèi)的向量存儲器和核外存儲器的通信需求,本文設計了兩個高低優(yōu)先級的通用通道。它們支持矩陣轉(zhuǎn)置操作,解決了現(xiàn)有DSP不能直接支持矩陣轉(zhuǎn)置操作的難題。并且它們具有通道鏈接和參數(shù)連接的功能,能夠滿足某些復雜數(shù)據(jù)流的傳輸需求。3.為滿足VM、ASRAM、DDR3和從天線收發(fā)數(shù)據(jù)的專用外設的通信需求,本文設計了AXI專用通道。它既可與AXI主機相連,也可與AXI從機相連,使用靈活。4.為滿足仿真/調(diào)試部件ET對DSP存儲空間的讀寫需求,本文設計了一個ET專用通道。它支持多個數(shù)據(jù)的讀寫并且尋址方式多樣,便于以后ET功能的擴展。5.為保證設計的功能正確性,本文采用模擬驗證和基于斷言的驗證兩種驗證方法對設計進行了充分驗證。模擬驗證分為模塊級、部件級和系統(tǒng)級三個層次,統(tǒng)計的代碼覆蓋率滿足要求。基于斷言的驗證對接口協(xié)議和總線仲裁進行了驗證。驗證結(jié)果表明,DMA控制器的功能正確,滿足系統(tǒng)設計要求。6.基于45nm工藝庫對設計進行了邏輯綜合。綜合結(jié)果表明,DMA控制器工作頻率可達到800MHz以上,總面積為165411.5um2,總功耗為65.97 m W,達到了預期設計目標。
[Abstract]:YHFT-Matrix is a high performance floating point DSP (Digital Signal Processor) soft core with independent intellectual property for wireless communication, video and image processing developed by the University of National Defense Science and Technology. In order to solve the data supply problem of DSP, this paper designs a powerful component of moving data, called Direct memory access Controller (Direct Memory Access Controller,DMAC). The main work and results of this paper include: 1. The architecture and application requirements of the DSP are analyzed in depth. The overall structure design of a multi-channel and multi-bus DMA controller is completed, and the address of the DMA controller is parameterized. In order to meet the communication requirements of vector memory and external memory in the core, two common channels with high priority and high priority are designed in this paper. They support matrix transpose operation and solve the problem that existing DSP can not directly support matrix transpose operation. And they have the function of channel link and parameter connection, which can meet the transmission requirement of some complex data stream. 3. In order to meet the communication requirements of VM,ASRAM,DDR3 and special peripheral equipment for receiving and transmitting data from antenna, a special channel for AXI is designed in this paper. It can be connected to both the AXI host and the AXI slave, using flexible. 4. 4. In order to meet the requirement of reading and writing DSP storage space in ET, a special ET channel is designed in this paper. It supports multiple data reading, writing and addressing in a variety of ways, making it easy to extend the ET function in the future. 5. In order to ensure the functional correctness of the design, two verification methods, simulation verification and assertion based verification, are used to fully verify the design. Simulation verification is divided into three levels: module level, component level and system level. Verification based on assertion verifies interface protocol and bus arbitration. The verification results show that the function of DMA controller is correct and meets the requirement of system design. The logic synthesis of the design based on 45nm process library is carried out. The results show that the operating frequency of the controller can reach above 800MHz, the total area is 165411.5um2, the total power consumption is 65.97mW, and the expected design goal is achieved.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP333
，

本文編號：2255425