通用高性能微處理器的低功耗片上存儲系統(tǒng)研究
發(fā)布時間：2018-09-19 17:54
【摘要】：微處理器是片上系統(tǒng)（SoC）的核心,其低功耗設(shè)計對整個系統(tǒng)的重要性突出，而低功耗片上存儲系統(tǒng)的設(shè)計是最重要的研究領(lǐng)域之一，是實現(xiàn)低功耗微處理器的關(guān)鍵，因為超過60％的功耗在微處理器芯片的片上存儲系統(tǒng)中產(chǎn)生。 本文給出一種新型SRAM單元，，在讀操作過程中其數(shù)據(jù)具有較高的穩(wěn)定性，并且與傳統(tǒng)4管SRAM單元和6管SRAM單元相比具有更高的靜態(tài)噪聲容限，另外也彌補(bǔ)了傳統(tǒng)SRAM存在的兩方面缺陷。7管SRAM單元的數(shù)據(jù)讀寫路徑獨立，讀寫過程的相互干擾也由此避免。特別地，由于去除了從位線到存儲節(jié)點的直接通路，到達(dá)了隔離數(shù)據(jù)的目的。因此，外部噪聲不易破壞SRAM單元中的數(shù)據(jù)，從而提高SRAM單元抗外部噪聲的性能和數(shù)據(jù)穩(wěn)定度。仿真采用TSMC1-Poly6-Metals0.18-μm CMOS工藝，在給定模式下，V_(DD)=1.8V，溫度T=25℃。仿真表明，7管SRAM單元的讀靜態(tài)噪聲容限高達(dá)1.43V，比傳統(tǒng)4管和6管SRAM單元顯著增加1.6倍和0.31倍。 為了實現(xiàn)低功耗的目的，本文給出一種只含一位標(biāo)識的片上指令Cache。在微處理器中，由于片上I-Cache大面積與極高頻率地被讀取，其功耗占據(jù)相當(dāng)大部分。為了減少片上I-Cache的功耗，本文研究了一種一位標(biāo)識符的片上I-Cache。改進(jìn)后的I-Cache在面積上顯著減少，Cache標(biāo)識部分只保留最根本的一位。同時，為了配合只含一位標(biāo)識的片上I-Cache，使程序依然有效地執(zhí)行，本文又給出一種Cache操作控制機(jī)制。對于大多數(shù)應(yīng)用程序而言，一位標(biāo)識Cache可以達(dá)到與傳統(tǒng)全標(biāo)識Cache相似的性能，但由于Cache面積急劇減少，并衍生規(guī)模更小的標(biāo)識(Tag)陣列與更少的Tag比較電路，所以可以有效降低功耗。
[Abstract]:Microprocessor is the core of on-chip system (SoC), and its low power design is very important to the whole system. The design of low power on-chip memory system is one of the most important research fields, and it is the key to realize low power microprocessor. Because more than 60% of the power consumption is generated in the on-chip memory system of the microprocessor chip. In this paper, a new type of SRAM unit is presented. Its data is stable in the process of reading operation, and it has higher static noise tolerance than the traditional 4-tube SRAM unit and 6-tube SRAM unit. In addition, it also makes up for the two defects of traditional SRAM. 7. The data read-write path of SRAM cell is independent, and the mutual interference of reading and writing process is avoided. In particular, the purpose of isolating data is achieved by removing the direct path from bit lines to storage nodes. Therefore, the external noise is not easy to destroy the data in the SRAM unit, thus improving the performance and data stability of the SRAM unit against external noise. The TSMC1-Poly6-Metals0.18- 渭 m CMOS process is used in the simulation. Under the given mode, the temperature of V _ (DD) is 1.8 V and the temperature is 25 鈩
本文編號：2250889
[Abstract]:Microprocessor is the core of on-chip system (SoC), and its low power design is very important to the whole system. The design of low power on-chip memory system is one of the most important research fields, and it is the key to realize low power microprocessor. Because more than 60% of the power consumption is generated in the on-chip memory system of the microprocessor chip. In this paper, a new type of SRAM unit is presented. Its data is stable in the process of reading operation, and it has higher static noise tolerance than the traditional 4-tube SRAM unit and 6-tube SRAM unit. In addition, it also makes up for the two defects of traditional SRAM. 7. The data read-write path of SRAM cell is independent, and the mutual interference of reading and writing process is avoided. In particular, the purpose of isolating data is achieved by removing the direct path from bit lines to storage nodes. Therefore, the external noise is not easy to destroy the data in the SRAM unit, thus improving the performance and data stability of the SRAM unit against external noise. The TSMC1-Poly6-Metals0.18- 渭 m CMOS process is used in the simulation. Under the given mode, the temperature of V _ (DD) is 1.8 V and the temperature is 25 鈩
本文編號：2250889
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2250889.html
最近更新
教材專著
