【摘要】：隨著嵌入式系統(tǒng)的功能日趨強大,其應用范圍正在不斷擴展到生活中的各個領域,使嵌入式處理器已經(jīng)成為當前計算機科學的一個研究熱點。然而,由于嵌入式處理器結構的日益復雜化,導致直接進行嵌入式處理器的設計實現(xiàn)和與其相配套的系統(tǒng)軟件的開發(fā),需要消耗大量的時間和成本。 SPARC v8是一個RISC體系結構,具有高性能和可擴展的特性,在國防航天等工業(yè)中大量使用基于該體系結構的嵌入式處理器。本文基于SPARC v8的體系結構設計并實現(xiàn)了嵌入式處理器的仿真平臺,通過該仿真平臺可以對要設計的處理器進行驗證,進行相關軟件的開發(fā)測試。同時,該仿真平臺通過定義的擴展接口,允許開發(fā)者和測試者自定義協(xié)處理器模塊。 本文通過對SPARC v8體系結構進行詳細的分析和總結,將仿真平臺的架構劃分為內(nèi)核模塊、指令執(zhí)行模塊、存儲單元仿真模塊、公共函數(shù)模塊和接口函數(shù)模塊。該仿真平臺是一個指令級仿真器,采用指令隊列來模擬流水線結構,并且添加了模擬時鐘來模擬每個指令在執(zhí)行過程中所用的時鐘周期。考慮到不同用戶對嵌入式處理器有不同的需求,本文在嵌入式處理器已有的功能的基礎上,設計并實現(xiàn)了可擴展協(xié)處理器單元,并以循環(huán)冗余校驗(CRC)單元作為例子,介紹如何通過調(diào)用相關的函數(shù)接口來實現(xiàn)自定義的協(xié)處理器模塊。 最后,本文詳細闡述了該仿真平臺在linux操作系統(tǒng)下的實現(xiàn)過程。該仿真平臺可以裝載由編譯器(例如sparc-elf-3.4.4)生成的可執(zhí)行文件,然后使用定義的debug命令調(diào)試運行。該仿真平臺已經(jīng)在某嵌入式處理器的設計開發(fā)中應用。
[Abstract]:With the increasingly powerful function of embedded system, its application scope is expanding to every field of life, so embedded processor has become a research hotspot in computer science. However, due to the complexity of embedded processor architecture, the design and implementation of embedded processor and the development of corresponding system software are carried out directly. SPARC v8 is a RISC architecture with high performance and extensibility. It is widely used in defense and spaceflight industries, such as embedded processors based on this architecture. Based on the architecture of SPARC v8, the simulation platform of embedded processor is designed and implemented in this paper. The simulation platform can be used to verify the processor to be designed and to develop and test the related software. At the same time, the platform allows developers and testers to customize coprocessor modules by defining extended interfaces. By analyzing and summarizing the architecture of SPARC v8 in detail, the architecture of the simulation platform is divided into kernel module, instruction execution module, memory unit simulation module, common function module and interface function module. The simulation platform is an instruction level simulator which uses instruction queue to simulate pipelined structure and adds an analog clock to simulate the clock period used in the execution of each instruction. Considering that different users have different requirements for embedded processors, this paper designs and implements scalable coprocessor units on the basis of existing functions of embedded processors, and takes cyclic redundancy check (CRC) unit as an example. This paper introduces how to implement the custom coprocessor module by calling the related function interface. Finally, this paper describes the implementation of the simulation platform under the linux operating system in detail. The simulation platform can load executable files generated by compiler (such as sparc-elf-3.4.4), and then debug run with defined debug command. The simulation platform has been applied in the design and development of an embedded processor.
【學位授予單位】：華北電力大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP391.9;TP368.1

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相關期刊論文 前8條

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本文編號：2244299