發(fā)布時(shí)間：2018-09-15 19:36

【摘要】：隨著嵌入式系統(tǒng)的功能日趨強(qiáng)大,其應(yīng)用范圍正在不斷擴(kuò)展到生活中的各個(gè)領(lǐng)域,使嵌入式處理器已經(jīng)成為當(dāng)前計(jì)算機(jī)科學(xué)的一個(gè)研究熱點(diǎn)。然而,由于嵌入式處理器結(jié)構(gòu)的日益復(fù)雜化,導(dǎo)致直接進(jìn)行嵌入式處理器的設(shè)計(jì)實(shí)現(xiàn)和與其相配套的系統(tǒng)軟件的開(kāi)發(fā),需要消耗大量的時(shí)間和成本。 SPARC v8是一個(gè)RISC體系結(jié)構(gòu),具有高性能和可擴(kuò)展的特性,在國(guó)防航天等工業(yè)中大量使用基于該體系結(jié)構(gòu)的嵌入式處理器。本文基于SPARC v8的體系結(jié)構(gòu)設(shè)計(jì)并實(shí)現(xiàn)了嵌入式處理器的仿真平臺(tái),通過(guò)該仿真平臺(tái)可以對(duì)要設(shè)計(jì)的處理器進(jìn)行驗(yàn)證,進(jìn)行相關(guān)軟件的開(kāi)發(fā)測(cè)試。同時(shí),該仿真平臺(tái)通過(guò)定義的擴(kuò)展接口,允許開(kāi)發(fā)者和測(cè)試者自定義協(xié)處理器模塊。 本文通過(guò)對(duì)SPARC v8體系結(jié)構(gòu)進(jìn)行詳細(xì)的分析和總結(jié),將仿真平臺(tái)的架構(gòu)劃分為內(nèi)核模塊、指令執(zhí)行模塊、存儲(chǔ)單元仿真模塊、公共函數(shù)模塊和接口函數(shù)模塊。該仿真平臺(tái)是一個(gè)指令級(jí)仿真器,采用指令隊(duì)列來(lái)模擬流水線結(jié)構(gòu),并且添加了模擬時(shí)鐘來(lái)模擬每個(gè)指令在執(zhí)行過(guò)程中所用的時(shí)鐘周期�？紤]到不同用戶對(duì)嵌入式處理器有不同的需求,本文在嵌入式處理器已有的功能的基礎(chǔ)上,設(shè)計(jì)并實(shí)現(xiàn)了可擴(kuò)展協(xié)處理器單元,并以循環(huán)冗余校驗(yàn)(CRC)單元作為例子,介紹如何通過(guò)調(diào)用相關(guān)的函數(shù)接口來(lái)實(shí)現(xiàn)自定義的協(xié)處理器模塊。 最后,本文詳細(xì)闡述了該仿真平臺(tái)在linux操作系統(tǒng)下的實(shí)現(xiàn)過(guò)程。該仿真平臺(tái)可以裝載由編譯器(例如sparc-elf-3.4.4)生成的可執(zhí)行文件,然后使用定義的debug命令調(diào)試運(yùn)行。該仿真平臺(tái)已經(jīng)在某嵌入式處理器的設(shè)計(jì)開(kāi)發(fā)中應(yīng)用。
[Abstract]:With the increasingly powerful function of embedded system, its application scope is expanding to every field of life, so embedded processor has become a research hotspot in computer science. However, due to the complexity of embedded processor architecture, the design and implementation of embedded processor and the development of corresponding system software are carried out directly. SPARC v8 is a RISC architecture with high performance and extensibility. It is widely used in defense and spaceflight industries, such as embedded processors based on this architecture. Based on the architecture of SPARC v8, the simulation platform of embedded processor is designed and implemented in this paper. The simulation platform can be used to verify the processor to be designed and to develop and test the related software. At the same time, the platform allows developers and testers to customize coprocessor modules by defining extended interfaces. By analyzing and summarizing the architecture of SPARC v8 in detail, the architecture of the simulation platform is divided into kernel module, instruction execution module, memory unit simulation module, common function module and interface function module. The simulation platform is an instruction level simulator which uses instruction queue to simulate pipelined structure and adds an analog clock to simulate the clock period used in the execution of each instruction. Considering that different users have different requirements for embedded processors, this paper designs and implements scalable coprocessor units on the basis of existing functions of embedded processors, and takes cyclic redundancy check (CRC) unit as an example. This paper introduces how to implement the custom coprocessor module by calling the related function interface. Finally, this paper describes the implementation of the simulation platform under the linux operating system in detail. The simulation platform can load executable files generated by compiler (such as sparc-elf-3.4.4), and then debug run with defined debug command. The simulation platform has been applied in the design and development of an embedded processor.
【學(xué)位授予單位】：華北電力大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP391.9;TP368.1

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本文編號(hào)：2244299