【摘要】：近年來(lái),傳統(tǒng)驅(qū)動(dòng)單處理器計(jì)算性能提升的技術(shù)逐步接近極限,在未來(lái)一段時(shí)間內(nèi)CMP技術(shù)將做為提升處理器性能的主要手段。但隨著單芯片上集成核心數(shù)量的增加，核間通信壓力越來(lái)越大，如何充分利用片上資源，構(gòu)建高效的片上通信網(wǎng)絡(luò)，已成為計(jì)算機(jī)體系結(jié)構(gòu)研究者們的重要探索方向。由于體系結(jié)構(gòu)相似，片上網(wǎng)絡(luò)所采用的技術(shù)多來(lái)自傳統(tǒng)的片間網(wǎng)絡(luò)，但片上環(huán)境的變化，導(dǎo)致這些技術(shù)不能簡(jiǎn)單地移植到片上，必須對(duì)其進(jìn)行改進(jìn)優(yōu)化以適應(yīng)片上平臺(tái)新的物理特性和應(yīng)用需求。 死鎖恢復(fù)技術(shù)可以解決完全自適應(yīng)路由中的死鎖問(wèn)題，但在片間網(wǎng)絡(luò)中，由于硬件條件的限制，普遍存在精確檢測(cè)難，解鎖代價(jià)大等問(wèn)題，限制了死鎖恢復(fù)技術(shù)的發(fā)展。本文在對(duì)目前采取的各種解決死鎖問(wèn)題的策略進(jìn)行了全面的分析的基礎(chǔ)上，結(jié)合片上硬件環(huán)境的新特點(diǎn)，引入了精確回路定向（Accurate CycleForwarding，ACF）思想。并在此基礎(chǔ)上提出了一種基于拓?fù)渑判颍═opology OrderDetection，TOD）的精確死鎖檢測(cè)機(jī)制和一種基于彈性信用（Elastic Credit Transfer，ECT）的死鎖解鎖機(jī)制。用極小的硬件開(kāi)銷(xiāo)實(shí)現(xiàn)了死鎖恢復(fù)，，解決了上述問(wèn)題。 本文完成了驗(yàn)證平臺(tái)HNRsim，并對(duì)HNRsim模擬器編碼針對(duì)本文提出思路的進(jìn)行了優(yōu)化。驗(yàn)證平臺(tái)支持配置大小的Mesh和Torus網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu)，支持多種路由方式和通信模型，可自由修改路由方式以及通訊模式，網(wǎng)絡(luò)中交換方式，報(bào)文長(zhǎng)度，分片大小，注入率等關(guān)鍵參數(shù)均可以根據(jù)使用者的需求配置。在此平臺(tái)上對(duì)新技術(shù)進(jìn)行了測(cè)試。 本文基于上述驗(yàn)證平臺(tái)，對(duì)TOD技術(shù)和ECT技術(shù)進(jìn)行了時(shí)鐘精度的模擬驗(yàn)證，并與其他相關(guān)技術(shù)在不同注入率及不同通信模式下進(jìn)行了性能上和硬件開(kāi)銷(xiāo)上的比較�？傮w來(lái)看，在性能上相較于采用靜態(tài)維序路由技術(shù)有較大提升，平均可以減少70%以上的傳輸延遲。而相比于傳統(tǒng)的時(shí)間閾值檢測(cè)搭配DISHA的死鎖恢復(fù)技術(shù)也有明顯的性能提升。此外在硬件開(kāi)銷(xiāo)方面，總體相比無(wú)死鎖恢復(fù)技術(shù)的基本網(wǎng)絡(luò)面積僅僅增加了13%，而相比DISHA技術(shù)節(jié)省了27%的面積開(kāi)銷(xiāo)。
[Abstract]:In recent years, the traditional drive single-processor computing performance improvement technology is gradually approaching the limit, in the future, CMP technology will be the main means to improve processor performance. However, with the increase of the number of integrated cores on a single chip, the pressure of inter-core communication is increasing. How to make full use of on-chip resources to build efficient on-chip communication networks has become an important research direction for computer architecture researchers. Because of the similar architecture, most of the technologies used in the on-chip network come from the traditional inter-chip network, but because of the change of the on-chip environment, these technologies can not be simply transplanted to the chip. It must be improved and optimized to meet the new physical characteristics and application requirements of the on-chip platform. Deadlock recovery technology can solve the deadlock problem in fully adaptive routing, but in the inter-chip network, due to the limitation of hardware conditions, there are many problems such as the difficulty of accurate detection and the high cost of unlocking, which limits the development of deadlock recovery technology. In this paper, based on the comprehensive analysis of various strategies adopted to solve the deadlock problem and the new characteristics of the on-chip hardware environment, the idea of precise loop orientation (Accurate CycleForwarding,ACF) is introduced. On this basis, an accurate deadlock detection mechanism based on topological ordering (Topology OrderDetection,TOD) and a deadlock unlocking mechanism based on elastic credit (Elastic Credit Transfer,ECT are proposed. The deadlock recovery is realized with minimal hardware overhead, which solves the above problem. This paper completes the verification platform HNRsim, and optimizes the coding of HNRsim simulator. The verification platform supports the configuration size of Mesh and Torus network topologies, supports various routing modes and communication models, freely modifies routing and communication modes, exchanges in networks, message length, slice size, and so on. The key parameters, such as injection rate, can be configured according to the user's requirements. The new technology is tested on this platform. Based on the above verification platform, this paper simulates the clock accuracy of TOD and ECT technologies, and compares the performance and hardware overhead with other related technologies in different injection rates and different communication modes. In general, compared with the static dimensionality routing technology, the performance can be greatly improved, and the average transmission delay can be reduced by more than 70%. Compared with the traditional time threshold detection and DISHA deadlock recovery technology also has a significant performance improvement. In addition, compared with the deadlock-free recovery technology, the basic network area is only increased by 13%, while compared with the DISHA technology, the total area cost is saved by 27%.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP303

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 羅欣武;戎蒙恬;劉文江;;片上系統(tǒng)中外部存儲(chǔ)控制器的設(shè)計(jì)與優(yōu)化[J];上海交通大學(xué)學(xué)報(bào);2007年06期

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