【摘要】：在航天嵌入式處理機(jī)應(yīng)用中，采用通用處理器或?qū)Ｓ眉呻娐罚ˋSIC）的實(shí)現(xiàn)方式均不能同時(shí)兼顧性能和靈活性的要求。專用指令集處理器（ASIP）平衡了專用集成電路的高性能和通用處理器的可編程特性，是針對(duì)某一特定應(yīng)用或某一領(lǐng)域應(yīng)用而專門(mén)設(shè)計(jì)的微處理器。本文圍繞航天嵌入式應(yīng)用專用指令集處理器的設(shè)計(jì)與實(shí)現(xiàn)做了以下三個(gè)方面的研究： 首先，選定SPARC架構(gòu)作為專用指令集處理器實(shí)現(xiàn)的基礎(chǔ)，并根據(jù)專用指令集處理器的設(shè)計(jì)方法以及FPGA硬件資源的特性對(duì)SPARC架構(gòu)的系統(tǒng)結(jié)構(gòu)和指令集結(jié)構(gòu)做出了一定的精簡(jiǎn)與優(yōu)化，進(jìn)而提取出了一套專用的指令集。 其次，為了提高專用指令集處理器的性能，根據(jù)FPGA的資源特點(diǎn)，，專用指令集處理器采用了五級(jí)流水線的實(shí)現(xiàn)結(jié)構(gòu)，并通過(guò)數(shù)據(jù)定向的技術(shù)和分支未執(zhí)行的策略來(lái)分別解決流水線中的數(shù)據(jù)冒險(xiǎn)和控制冒險(xiǎn)。 最后，以Xilinx公司的FPGA Vertex-6XC6VLX240T為載體，對(duì)整個(gè)ASIP進(jìn)行了系統(tǒng)仿真和綜合驗(yàn)證，同時(shí)在該專用指令集處理器上實(shí)現(xiàn)了冒泡排序算法和FIR數(shù)字濾波器這兩個(gè)應(yīng)用。由仿真與驗(yàn)證結(jié)果可知，本文所設(shè)計(jì)的專用指令集處理器能夠達(dá)到預(yù)期功能和時(shí)序要求，并且由于電路結(jié)構(gòu)緊湊，在單片F(xiàn)PGA內(nèi)能夠集成多個(gè)專用指令集處理器核實(shí)現(xiàn)并行處理。
[Abstract]:In the application of aerospace embedded processor, the implementation of general purpose processor or ASIC (ASIC) can not meet the requirements of performance and flexibility at the same time. The ASIP processor (ASIP) balances the high performance of ASIC and the programmable characteristic of general-purpose processor. It is a microprocessor specially designed for a particular application or application in a certain field. This paper focuses on the design and implementation of the special instruction set processor for aerospace embedded application. Firstly, the SPARC architecture is selected as the basis of the implementation of the special instruction set processor. According to the design method of special instruction set processor and the characteristic of FPGA hardware resource, the system structure and instruction set structure of SPARC architecture are simplified and optimized, and a set of special instruction sets is extracted. Secondly, in order to improve the performance of the special instruction set processor, according to the resource characteristics of FPGA, the special instruction set processor adopts a five-stage pipeline structure. Data-oriented techniques and branch-unexecuted strategies are used to solve data risk-taking and control risks in pipeline respectively. Finally, the system simulation and comprehensive verification of the whole ASIP are carried out with the FPGA Vertex-6XC6VLX240T of Xilinx Company as the carrier. At the same time, the bubbling sorting algorithm and the FIR digital filter are implemented on the special instruction set processor. The simulation and verification results show that the designed special instruction set processor can achieve the expected function and timing requirements, and because of the compact circuit structure, it can integrate multiple special instruction set processor cores to realize parallel processing in a single FPGA.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前2條

1 吳俊;基于RISC結(jié)構(gòu)的ASIP設(shè)計(jì)[D];浙江大學(xué);2002年

2 張海南;基于FPGA的高性能32位浮點(diǎn)FFT IP核的開(kāi)發(fā)[D];廣西大學(xué);2008年

本文編號(hào)：2238798