【摘要】：近年來,串行傳輸方式越來越受到重視,已經(jīng)有不少串行傳輸取代并行傳輸?shù)睦樱篣SB取代了IEEE1284,SATA取代了PATA,PCI EXPRESS取代PCI等等。可以預(yù)見,未來串行傳輸將會成為數(shù)據(jù)傳輸方式的主流。 DDR SDRAM已經(jīng)發(fā)展到了第三代,傳輸速度更快,功耗更低,應(yīng)用范圍更廣。但是隨著性能的不斷提升,它的引腳也越來越多,成本越來越高。當(dāng)并行傳輸方式為提高數(shù)據(jù)傳輸速率而增加端口引腳時,造成了成本的增加和信號間干擾的加劇,DDR SDRAM也陷入了同樣的困境。 本文首先比較了不同的存儲器的發(fā)展和優(yōu)劣,在此基礎(chǔ)上提出了一種新型的串行DDR SDRAM存儲器架構(gòu)SDDR。SDDR的設(shè)計(jì)思想主要有三部分： 1.將存儲器的控制命令、地址、數(shù)據(jù)等信息打包,以消息包的方式傳遞信息,而不再是通過并行總線直接對存儲器進(jìn)行訪問。 2.將原來存儲器的控制器分為兩部分,一部分連接主機(jī),作為SDDR的控制器,另一部分作為存儲器的一部分,完成數(shù)據(jù)的解析等操作。 3.在SDDR控制器與控制接口之間采用單向串行只寫總線(OWOSB, One-way Write-Only Serial Bus)傳遞信息,信息只能沿著一個方向傳輸,而且OWOSB只用到2根,一根為上行總線,一根為下行總線。 本文完成了SDDR控制器和控制接口的設(shè)計(jì),定義了串行只寫總線OWOSB的消息傳遞幀格式,引入一根狀態(tài)總線解決數(shù)據(jù)沖突,結(jié)合現(xiàn)有資源,完成了仿真驗(yàn)證工作。 在查閱大量資料后,完成SDDR SDRAM硬件測試平臺原理圖的設(shè)計(jì),選取了芯片,完成電路板的布線和器件的焊接,采用濾波電路和磁珠隔離等提高了信號的抗干擾能力。最終完成了6層電路板的設(shè)計(jì)和調(diào)試,完成了SDDR架構(gòu)的驗(yàn)證。
[Abstract]:In recent years, more and more attention has been paid to serial transmission. There are many examples of serial transmission replacing parallel transmission. IEEE1284,SATA replaces IEEE1284,SATA instead of PATA,PCI EXPRESS instead of PCI and so on. It can be predicted that the future serial transmission will become the mainstream of data transmission. DDR SDRAM has developed to the third generation, the transmission speed is faster, the power consumption is lower, the application scope is wider. However, with the continuous improvement of performance, it has more and more pins and higher cost. When the parallel transmission mode increases the port pin to improve the data transmission rate, the cost increases and the inter-signal interference intensifies. In this paper, the development and advantages of different memory are compared at first, and then a new serial DDR SDRAM memory architecture SDDR.SDDR is proposed in this paper. There are three main parts: 1. The control command, address, data and other information of the memory are packed, and the information is transmitted by the message packet, instead of directly accessing the memory through the parallel bus. 2. 2. The controller of the original memory is divided into two parts, one is connected to the host computer as the controller of SDDR, the other part is part of the memory to complete the operation of data parsing and so on. 3. A one-way serial write only bus (OWOSB, One-way Write-Only Serial Bus) is used to transmit information between the SDDR controller and the control interface. The information can only be transmitted along one direction, and only two OWOSB are used, one is an uplink bus and the other is a downlink bus. In this paper, the design of SDDR controller and control interface is completed, the message passing frame format of serial write-only bus OWOSB is defined, a state bus is introduced to solve the data conflict, and the simulation and verification work is completed with the existing resources. After consulting a lot of data, the schematic diagram of SDDR SDRAM hardware test platform is designed, the chip is selected, the wiring and welding of the circuit board are completed, and the anti-interference ability of the signal is improved by using filter circuit and magnetic bead isolation. Finally, the design and debugging of the six-layer circuit board are completed, and the SDDR architecture is verified.
【學(xué)位授予單位】：太原理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333

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本文編號：2236632