【摘要】：XDSP64是我校自主研制的一款高性能定點(diǎn)DSP芯片，該款芯片擁有可配置增強(qiáng)型主機(jī)接口（HPI）（數(shù)據(jù)總線為32或16位）、異步傳輸模式(ATM)的通用測試及操作物理層接口（UTOPIA）、EMIF、多通道串口以及定時器等多種外設(shè)接口。本課題基于高性能XDSP64芯片的配套驗證開發(fā)系統(tǒng)要求，實現(xiàn)了對片上多種外設(shè)接口（包括UTOPIA、HPI等）的功能驗證與時序測試。 為了更好的研制、測試與應(yīng)用開發(fā)這些外設(shè)接口，使得XDSP64芯片達(dá)到更高的設(shè)計要求，本文設(shè)計了基于XDSP64芯片多外設(shè)接口的軟硬件協(xié)同仿真平臺，以實現(xiàn)外部主機(jī)與DSP芯片之間的多渠道高速數(shù)據(jù)通信機(jī)制（HPI通信、UTOPIA通信等）。 本文首先在廣泛調(diào)研HPI、UTOPIA等接口在DSP控制領(lǐng)域的實際應(yīng)用的基礎(chǔ)上，深入了解了XDSP64的體系結(jié)構(gòu)，并對仿真平臺的系統(tǒng)功能進(jìn)行了全面分析。結(jié)合XDSP64芯片的接口仿真開發(fā)要求，合理構(gòu)建了由主機(jī)通信系統(tǒng)和接口主控制器兩部分構(gòu)成的整個仿真平臺系統(tǒng)架構(gòu)，并分別提出了平臺系統(tǒng)的軟件、硬件設(shè)計的目標(biāo)。 接著本文在充分理解USB2.0接口協(xié)議基礎(chǔ)之上，基于Cypress公司的EZ-USBFX2芯片，設(shè)計了精煉的主機(jī)通信系統(tǒng)，此系統(tǒng)有效利用了USB2.0480Mb/s的高速數(shù)據(jù)傳輸特點(diǎn)并通過對固件、驅(qū)動程序以及仿真應(yīng)用軟件的設(shè)計，為整個仿真系統(tǒng)提供了功能完整、操作靈活的主機(jī)操作平臺。 同時，本文還設(shè)計了一套可視化的主機(jī)應(yīng)用軟件。將復(fù)雜的接口協(xié)議訪問簡化為視圖操作，實現(xiàn)了良好的人機(jī)交互。 然后，本文深入研究了XDSP64的外設(shè)接口協(xié)議。基于FPGA設(shè)計了XDSP64芯片的HPI接口、UTOPIA接口等多接口主控制器。采用了異步主機(jī)接口方法來實現(xiàn)主控制器與主機(jī)通信系統(tǒng)的通信協(xié)議，以增強(qiáng)仿真平臺的兼容性與可擴(kuò)展性。在主控制器設(shè)計中設(shè)置了專用配置寄存器，以此實現(xiàn)對XDSP64的內(nèi)、外存空間訪問、寄存器操作、XDSP64的自舉以及不同接口方式的數(shù)據(jù)通信。 最后本文對系統(tǒng)進(jìn)行了全面調(diào)試和驗證，結(jié)果表明此仿真平臺系統(tǒng)能夠正確、穩(wěn)定地運(yùn)行，完成了對XDSP64芯片HPI接口和UTOPIA接口功能的仿真和相關(guān)時序參數(shù)的測試，達(dá)到了設(shè)計的目標(biāo)。
[Abstract]:XDSP64 is a high performance fixed-point DSP chip developed by our university. The chip has a configurable enhanced host interface (HPI) (data bus is 32 or 16 bits), asynchronous transmission mode (ATM) general test and operation physical layer interface (UTOPIA) EMIF, multi-channel serial port and timer and other peripheral interfaces. Based on the requirement of verification and development system of high performance XDSP64 chip, the function verification and timing test of various peripheral interfaces (including UTOPIA,HPI, etc.) on the chip are realized. In order to better research, test and develop these peripheral interfaces, make the XDSP64 chip achieve higher design requirements, this paper designed a hardware / software co-simulation platform based on XDSP64 chip multi-peripheral interface. In order to realize the multi-channel high-speed data communication mechanism between external host computer and DSP chip (HPI communication / Utopia communication etc.). Based on the extensive investigation of the practical application of HPI,UTOPIA and other interfaces in the field of DSP control, the architecture of XDSP64 is deeply understood in this paper, and the system functions of the simulation platform are analyzed. According to the requirements of interface simulation development of XDSP64 chip, the architecture of the whole simulation platform composed of host communication system and interface master controller is constructed reasonably, and the software and hardware design goals of the platform system are put forward respectively. On the basis of fully understanding the USB2.0 interface protocol, based on the EZ-USBFX2 chip of Cypress Company, this paper designs a refined host communication system, which effectively utilizes the high-speed data transmission characteristics of USB2.0480Mb/s and makes use of the firmware. The design of driver and simulation application provides the whole simulation system with a complete and flexible host operating platform. At the same time, this paper also designed a set of visual host application software. The complex interface protocol access is simplified to view operation, and good man-machine interaction is realized. Then, this paper deeply studies the peripheral interface protocol of XDSP64. Based on FPGA, the main controller with multiple interfaces such as HPI interface and UTOPIA interface of XDSP64 chip is designed. The asynchronous host interface method is used to realize the communication protocol between the master controller and the host computer communication system, so as to enhance the compatibility and extensibility of the simulation platform. A special configuration register is set up in the design of the main controller to access the internal and external memory space of the XDSP64, the register operation XDSP64 bootstrap and the data communication of different interfaces. Finally, the system is debugged and verified, and the results show that the system can run correctly and stably. The simulation of HPI interface and UTOPIA interface function of XDSP64 chip and the test of related timing parameters are completed. The goal of the design has been achieved.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP334.7

【共引文獻(xiàn)】

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1 周劍波;鞏憲鋒;王長松;孫宏林;;利用FPGA和USB總線的視頻圖像的采集與處理系統(tǒng)設(shè)計[J];北京科技大學(xué)學(xué)報;2006年09期

2 李金平;顏鋌;;便攜式電纜故障定位儀的設(shè)計研究[J];北京聯(lián)合大學(xué)學(xué)報(自然科學(xué)版);2006年02期

3 鄧在輝;丁莎;;斷言驗證技術(shù)在IP核驗證中的應(yīng)用[J];畢節(jié)學(xué)院學(xué)報;2008年04期

4 張松煒;張云麟;張治中;;基于FPGA的8E1時隙交換的數(shù)字交叉IP核的實現(xiàn)[J];重慶郵電學(xué)院學(xué)報(自然科學(xué)版);2006年02期

5 侯佰康;張昆侖;靖永志;;基于FPGA的高速磁浮列車懸浮間隙測量系統(tǒng)[J];傳感技術(shù)學(xué)報;2006年06期

6 靖永志;張昆侖;;高速磁浮列車懸浮氣隙測量系統(tǒng)的設(shè)計[J];傳感器技術(shù);2005年12期

7 謝桂英;;E1/VC-4映射解映射系統(tǒng)的設(shè)計[J];中國城市經(jīng)濟(jì);2011年03期

8 趙紅梅,王召東;可編程邏輯器件FPGA與CPLD的發(fā)展與應(yīng)用一例[J];平頂山工學(xué)院學(xué)報;2005年04期

9 浦索明;羅漢文;樊迅;;高速M(fèi)IMO解調(diào)器的FPGA實現(xiàn)[J];電訊技術(shù);2006年06期

10 張福洪;肖懷鋒;方洪燦;鄧朝日;;基于Nios Ⅱ的UHF RFID讀寫器設(shè)計與實現(xiàn)[J];電訊技術(shù);2009年05期

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1 李燕斌;;AM調(diào)制度判別原理及其在話音靜噪處理中的應(yīng)用[A];全國第二屆嵌入式技術(shù)聯(lián)合學(xué)術(shù)會議論文集[C];2007年

2 張騁;楊力;蔡惠智;;并行DSP系統(tǒng)的FPGA設(shè)計[A];全國第二屆嵌入式技術(shù)聯(lián)合學(xué)術(shù)會議論文集[C];2007年

3 李鳳麟;鐘洪聲;;保密通信中RS編解碼的FPGA實現(xiàn)[A];2006中國西部青年通信學(xué)術(shù)會議論文集[C];2006年

4 錢偉康;虞菁;郭強(qiáng);;基于SPARTAN3E-FPGA的多重數(shù)字時鐘源的拓?fù)鋄A];全國第一屆嵌入式技術(shù)聯(lián)合學(xué)術(shù)會議論文集[C];2006年

5 陳亮;郝衛(wèi)東;李靜;陳e，

本文編號：2230444