一種兼容MCS-51指令集的高速M(fèi)CU的設(shè)計(jì)及實(shí)現(xiàn)
發(fā)布時(shí)間：2018-09-08 07:25
【摘要】：MCU（Micro Controller Unit，微控制單元）自面世以來(lái)在數(shù)字系統(tǒng)設(shè)計(jì)中占有重要的位置，具有集成度高、可編程性強(qiáng)的特點(diǎn)，廣泛用于工業(yè)控制和SoC（System on Chip，片上系統(tǒng)）等數(shù)字系統(tǒng)設(shè)計(jì)中。但是傳統(tǒng)上的8位MCU指令執(zhí)行效率通常低于20MIPS（Million Instruction per Second，百萬(wàn)指令每秒），限制了其在高速計(jì)算場(chǎng)合中的應(yīng)用。 本課題來(lái)自某公司 數(shù)�；旌蟂oC芯片設(shè)計(jì)‖項(xiàng)目，該項(xiàng)目需要一個(gè)執(zhí)行效率能達(dá)到50MIPS且兼容MCS-51指令集的MCU。所謂兼容MCS-51指令集是本MCU的指令集與MCS-51系列MCU指令集相同，可以使用普通的51開(kāi)發(fā)軟件（如Keil C51）進(jìn)行開(kāi)發(fā)。 本文首先介紹了MCS-51指令集，接著描述了本設(shè)計(jì)MCU的組織結(jié)構(gòu)，設(shè)計(jì)了5級(jí)流水線結(jié)構(gòu)，以單時(shí)鐘周期作為指令運(yùn)行單位，實(shí)現(xiàn)了MCU內(nèi)核的高速和高效率。在設(shè)計(jì)運(yùn)算單元時(shí)，本文設(shè)計(jì)了一個(gè)基于進(jìn)位保留的三輸入加法器，利用1個(gè)三輸入加法器設(shè)計(jì)了乘法器，，該乘法器只需要4個(gè)時(shí)鐘周期就能完成乘法運(yùn)算。 本文改進(jìn)了標(biāo)準(zhǔn)8051功耗管理模塊，該管理模塊不僅繼承了標(biāo)準(zhǔn)8051的IDLE和STOP模式，還新加入了SUSPEND模式和多時(shí)鐘源自由切換功能，這樣可以使用戶更有效的減少芯片功耗。 此外，本文采用TSMC0.18um工藝的Flash IP核作為程序存儲(chǔ)器，但是該IP只能支持最高30MHz的系統(tǒng)時(shí)鐘。本文對(duì)Flash驅(qū)動(dòng)模塊和邏輯控制進(jìn)行了改進(jìn)設(shè)計(jì)使該IP能用于50MHz的系統(tǒng)時(shí)鐘下。 最后，為了驗(yàn)證設(shè)計(jì)的正確性，本文搭建出基于握手協(xié)議的仿真測(cè)試平臺(tái)，調(diào)用了OVM（Open Verification Methodlogy）庫(kù)。本文還搭建出基于Xilinx公司的Virtex-2Pro XC2VP30FPGA開(kāi)發(fā)板驗(yàn)證平臺(tái)，并給出了FPGA占用資源統(tǒng)計(jì)表。驗(yàn)證結(jié)果證明了設(shè)計(jì)的正確性，同時(shí)ISE綜合結(jié)果顯示該設(shè)計(jì)支持的時(shí)鐘頻率可以達(dá)到60MHz。 本文實(shí)現(xiàn)了兼容MCS-51指令集的MCU的高速設(shè)計(jì)，在50MHz時(shí)鐘下可以達(dá)到50MIPS的峰值。同目前市場(chǎng)上主流高速兼容MCS-51指令集MCU產(chǎn)品和文獻(xiàn)[18-21]相比，性能上有顯著提高。
[Abstract]:MCU (Micro Controller Unit, micro-control unit (MCU (Micro Controller Unit,) has played an important role in the design of digital system since its inception. It has the characteristics of high integration and strong programmability. It is widely used in the design of digital systems such as industrial control and SoC (System on Chip, on-chip systems. But the traditional 8-bit MCU instruction execution efficiency is usually lower than 20MIPS (Million Instruction per Second, million instruction per second, which limits its application in high-speed computing. This topic comes from a company's digital and analog hybrid SoC chip design project, which requires a MCU. that is efficient enough to execute 50MIPS and compatible with the MCS-51 instruction set. The so-called compatible MCS-51 instruction set is that the instruction set of this MCU is the same as the MCS-51 series MCU instruction set, and can be developed with common 51 development software (such as Keil C51). This paper first introduces the MCS-51 instruction set, then describes the organization structure of the MCU, and designs a 5-stage pipelined structure. The single clock cycle is used as the instruction unit to realize the high speed and high efficiency of the MCU kernel. In the design of the operation unit, a triple-input adder based on carry reservation is designed, and a multiplier is designed using a three-input adder. The multiplier needs only four clock cycles to complete the multiplication operation. This paper improves the standard 8051 power management module, which not only inherits the IDLE and STOP modes of standard 8051, but also adds the SUSPEND mode and the free switching function of multiple clock sources, which can effectively reduce the chip power consumption. In addition, the Flash IP core of TSMC0.18um process is used as program memory, but the IP can only support the highest 30MHz system clock. In this paper, the Flash driver module and logic control are improved so that the IP can be used in the system clock of 50MHz. Finally, in order to verify the correctness of the design, this paper builds a simulation test platform based on handshake protocol, and calls the OVM (Open Verification Methodlogy) library. The verification platform of Virtex-2Pro XC2VP30FPGA development board based on Xilinx company is also built in this paper, and the statistical table of FPGA occupation resources is given. The experimental results show that the design is correct, and the ISE synthesis results show that the clock frequency can reach 60 MHz. In this paper, the high speed design of MCU compatible with MCS-51 instruction set is realized, and the peak value of 50MIPS can be achieved under the 50MHz clock. Compared with the current mainstream high speed compatible MCS-51 instruction set MCU products and literature [18-21], the performance is significantly improved.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332;TN47
本文編號(hào)：2229801
[Abstract]:MCU (Micro Controller Unit, micro-control unit (MCU (Micro Controller Unit,) has played an important role in the design of digital system since its inception. It has the characteristics of high integration and strong programmability. It is widely used in the design of digital systems such as industrial control and SoC (System on Chip, on-chip systems. But the traditional 8-bit MCU instruction execution efficiency is usually lower than 20MIPS (Million Instruction per Second, million instruction per second, which limits its application in high-speed computing. This topic comes from a company's digital and analog hybrid SoC chip design project, which requires a MCU. that is efficient enough to execute 50MIPS and compatible with the MCS-51 instruction set. The so-called compatible MCS-51 instruction set is that the instruction set of this MCU is the same as the MCS-51 series MCU instruction set, and can be developed with common 51 development software (such as Keil C51). This paper first introduces the MCS-51 instruction set, then describes the organization structure of the MCU, and designs a 5-stage pipelined structure. The single clock cycle is used as the instruction unit to realize the high speed and high efficiency of the MCU kernel. In the design of the operation unit, a triple-input adder based on carry reservation is designed, and a multiplier is designed using a three-input adder. The multiplier needs only four clock cycles to complete the multiplication operation. This paper improves the standard 8051 power management module, which not only inherits the IDLE and STOP modes of standard 8051, but also adds the SUSPEND mode and the free switching function of multiple clock sources, which can effectively reduce the chip power consumption. In addition, the Flash IP core of TSMC0.18um process is used as program memory, but the IP can only support the highest 30MHz system clock. In this paper, the Flash driver module and logic control are improved so that the IP can be used in the system clock of 50MHz. Finally, in order to verify the correctness of the design, this paper builds a simulation test platform based on handshake protocol, and calls the OVM (Open Verification Methodlogy) library. The verification platform of Virtex-2Pro XC2VP30FPGA development board based on Xilinx company is also built in this paper, and the statistical table of FPGA occupation resources is given. The experimental results show that the design is correct, and the ISE synthesis results show that the clock frequency can reach 60 MHz. In this paper, the high speed design of MCU compatible with MCS-51 instruction set is realized, and the peak value of 50MIPS can be achieved under the 50MHz clock. Compared with the current mainstream high speed compatible MCS-51 instruction set MCU products and literature [18-21], the performance is significantly improved.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332;TN47
【參考文獻(xiàn)】
相關(guān)期刊論文 前4條
1 張俊謨;;單片機(jī)的發(fā)展與應(yīng)用[J];電子制作;2007年08期
2 牟剛,賀前華,江瑾;基于流水線結(jié)構(gòu)的高速嵌入式MCU設(shè)計(jì)[J];微電子學(xué);2004年04期
3 楊浩,林爭(zhēng)輝,李世煜;一種高效率MCS51兼容型微控制器內(nèi)核設(shè)計(jì)[J];微電子學(xué)與計(jì)算機(jī);2004年05期
4 戴宏,陳英濤,周開(kāi)鄰,權(quán)春娟;一種高性能MCS-51兼容微控制器的設(shè)計(jì)[J];云南大學(xué)學(xué)報(bào)(自然科學(xué)版);2005年06期
本文編號(hào)：2229801
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2229801.html
最近更新
教材專著
