【摘要】：在半導(dǎo)體技術(shù)飛速發(fā)展的今天,芯片的生產(chǎn)成本日益提高,這就使得我們提高芯片的良率顯得至關(guān)重要。同時(shí),在新的工藝節(jié)點(diǎn)下器件生產(chǎn)過程中帶來的偏差和仿真模型帶來的偏差都更容易引起生產(chǎn)出的芯片的參數(shù)與最初設(shè)計(jì)的值有所偏離,從而引入了熔絲技術(shù),由此我們可以利用電熔絲將芯片中的冗余電路替換掉失效的電路來提高良率,也可以對(duì)電路進(jìn)行重新組合來實(shí)現(xiàn)新的功能,還可以對(duì)芯片的某些參數(shù)進(jìn)行微調(diào)(TRIM)來提高芯片的性能。但是傳統(tǒng)的熔絲技術(shù)與主流的標(biāo)準(zhǔn)CMOS工藝并不兼容,導(dǎo)致成本偏高,而新興的電子可編程熔絲(eFuse)同時(shí)具有體積小、成本低、可以在封裝后再進(jìn)行編程等眾多的優(yōu)點(diǎn),所以電子可編程熔絲技術(shù)成為了一個(gè)新的研究熱點(diǎn)。 本文首先總結(jié)了eFuse當(dāng)前的國內(nèi)外研究現(xiàn)狀,然后基于中芯國際40納米低漏電CMOS工藝,從eFuse器件的類型選取入手,設(shè)計(jì)了并入并出的4K bits容量的eFuse IP,并成功地進(jìn)行了流片和測試,測試結(jié)果滿足設(shè)計(jì)要求。 因?yàn)閑Fuse的存儲(chǔ)器特性對(duì)IP的面積要求極為嚴(yán)苛,所以我們又通過了一個(gè)章節(jié)的篇幅來簡單介紹了一種能夠使大容量eFuse的IP節(jié)省約三成面積的優(yōu)化方案,其優(yōu)化效果顯著。
[Abstract]:With the rapid development of semiconductor technology, the production cost of chips is increasing day by day, which makes it very important for us to improve the yield of chips. At the same time, the deviation brought by the device production process under the new process node and the deviation brought by the simulation model are more likely to cause the parameters of the produced chip deviate from the original design value, so the fuse technology is introduced. As a result, we can use the electric fuse to replace the redundant circuits in the chip to improve the yield, and we can also recombine the circuits to achieve new functions. Some parameters of the chip can also be fine-tuned (TRIM) to improve the performance of the chip. However, the traditional fuse technology is not compatible with the mainstream standard CMOS process, which leads to high cost. The new electronic programmable fuse (eFuse) has many advantages, such as small size, low cost, and can be programmed after packaging. Therefore, electronic programmable fuse technology has become a new research hotspot. This paper first summarizes the current research situation of eFuse at home and abroad, then based on the SMIC 40 nm low leakage CMOS process, starting with the type selection of eFuse devices, designs the eFuse IP, with 4 K bits capacity and successfully carries out the flow sheet and test. The test results meet the design requirements. Because the memory characteristic of eFuse is very strict on the area of IP, we also introduce an optimization scheme which can save about 30% area of IP of large capacity eFuse through a chapter, and its optimization effect is remarkable.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TN432;TP333

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相關(guān)期刊論文 前1條

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本文編號(hào)：2226747