【摘要】：ARM處理器在現(xiàn)代的嵌入式電子產(chǎn)品中廣泛應(yīng)用，特別在通信、工業(yè)控制、自動化等行業(yè)更是應(yīng)用廣泛，目前ARM處理已經(jīng)成為嵌入式電子產(chǎn)品中使用做多的處理器。ARM JTAG仿真器作為ARM系統(tǒng)開發(fā)工具鏈的重要組成部分之一，對軟硬件開發(fā)和調(diào)試的效率、最終交付系統(tǒng)的穩(wěn)定性和健壯性、降低系統(tǒng)開發(fā)難度等方面都產(chǎn)生重要影響。 目前，JTAG仿真器已經(jīng)應(yīng)用于ARM系統(tǒng)的軟硬件研發(fā)工作之中，但高性能的JTAG調(diào)試器基本都由國外公司研發(fā)，因此價格昂貴，難以在一般開發(fā)者和小微企業(yè)普及；而國內(nèi)低價的JTAG調(diào)試器由于技術(shù)方案等問題往往性能較差且不夠穩(wěn)定，不支持一些高級調(diào)試功能（如高速下載、硬件斷點、數(shù)據(jù)斷點、FLASH編程等），無法滿足大規(guī)模軟件開發(fā)調(diào)試的需求。 本論文正是針對上述問題，，在深入分析TAP控制器、ARM EmbeddedICE等技術(shù)的基礎(chǔ)上，對GDB調(diào)試技術(shù)、RSP協(xié)議、μC/OS-II和LwIP等關(guān)鍵技術(shù)進行較深入的研究和試驗，設(shè)計采用AT91SAM9260處理器芯片的ARM JTAG仿真器，全面支持ARM7和ARM9系列內(nèi)核的調(diào)試、支持JTAG時鐘速率可編程，具有10/100M自適應(yīng)網(wǎng)絡(luò)、USB等通信接口。本研究課題主要內(nèi)容包括： 1.研究ARM JTAG調(diào)試原理，在對TAP控制器、EmbeddedICE邏輯、邊界掃描鏈進行分析的基礎(chǔ)之上，確定ARM JTAG仿真器的設(shè)計思路、方案以及基本實現(xiàn)方法。 2.在ARM JTAG調(diào)試原理的分析基礎(chǔ)之上，提出ARM JTAG的設(shè)計需求和規(guī)格單，并基于此提出以AT91SAM9260為處理器的硬件架構(gòu)的JTAG仿真器硬件設(shè)計方案，該方案支持10/100M自適應(yīng)以太網(wǎng)、RS232串口、USB等通信接口，支持寬輸入電壓范圍；針對被調(diào)試目標處理可能存在多種電壓的實際情況，設(shè)計了具有目標處理器電壓自適應(yīng)能力的JTAG接口；在給出設(shè)計方案的同時，針對關(guān)鍵部分的電路設(shè)計給出詳細的設(shè)計原理圖和器件選型依據(jù)和設(shè)計原理分析。 3.按照課題的設(shè)計需求和規(guī)格要求，設(shè)計基于μC/OS-II和LwIP的軟件整體架構(gòu)；針對需要支持高速下載，JTAG時鐘速率可編程等需求，設(shè)計了一套高性能的JTAG微指令邏輯；同時，對RSP協(xié)議、GDB命令解析器、JTAG調(diào)試命令接口等方面進行了比較詳細的靜態(tài)接口設(shè)計說明和動態(tài)流程設(shè)計說明。
[Abstract]:ARM processors are widely used in modern embedded electronic products, especially in communication, industrial control, automation and other industries. At present, ARM processing has become one of the most important components of the ARM system development tool chain, and the efficiency of software and hardware development and debugging has become the main part of the embedded electronic products, which uses the long processor .arm JTAG emulator as one of the most important parts of the ARM system development tool chain. The stability and robustness of the final delivery system, reducing the difficulty of system development and other aspects have an important impact. At present, JTAG emulator has been used in the research and development of ARM system, but the high performance JTAG debugger is developed by foreign companies, so it is expensive and difficult to be popularized in general developers and small and micro enterprises. However, the domestic low-cost JTAG debugger often has poor performance and unstable performance due to technical problems, so it does not support some advanced debugging functions (such as high-speed download, hardware breakpoint, etc.) Data breakpoint flash programming can not meet the needs of large-scale software development and debugging. In this paper, based on the analysis of TAP controller and arm EmbeddedICE technology, the key technologies of GDB debugging, such as GDB protocol, 渭 C/OS-II and LwIP, are studied and tested, and a ARM JTAG simulator using AT91SAM9260 processor chip is designed. It fully supports the debugging of ARM7 and ARM9 series kernels, supports the programmable clock rate of JTAG, and has 10 / 100M adaptive network communication interfaces such as USB. The main contents of this research include: 1. The principle of ARM JTAG debugging is studied. Based on the analysis of embedded ICE logic and boundary scan chain of TAP controller, the design idea, scheme and basic implementation method of ARM JTAG simulator are determined. 2. Based on the analysis of the debugging principle of ARM JTAG, the design requirements and specifications of ARM JTAG are presented, and the hardware design scheme of JTAG simulator based on AT91SAM9260 is presented. This scheme supports 10 / 100M adaptive Ethernet RS232 serial port and other communication interfaces, supports wide input voltage range, and designs a JTAG interface with the ability of adaptive voltage adaptation of target processor in view of the fact that there may be a variety of voltages to be processed by the target to be debugged. At the same time, the detailed design schematic diagram, device selection basis and design principle analysis are given for the circuit design of the key part. 3. According to the design requirements and specifications of the project, the software architecture based on 渭 C/OS-II and LwIP is designed, and a set of high-performance JTAG microinstruction logic is designed for the need to support high-speed download JTAG clock rate programmable. In this paper, the static interface design and dynamic flow design of RSP protocol are described in detail from the aspects of JTAG debug command interface and GDB command parser.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332

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