【摘要】：精簡指令集計(jì)算機(jī)(Reduced Instruction Set Computer, RISC)是1979年提出的一種先進(jìn)的處理器設(shè)計(jì)思想,其特點(diǎn)為優(yōu)先選取處理器中使用頻率最高的指令,并將指令的格式固定,指令的尋址方式減少。由于RISC簡單高效的優(yōu)點(diǎn),使其在提出之后就得到了業(yè)界的廣泛關(guān)注。目前在高性能服務(wù)器和嵌入式領(lǐng)域,90%的處理器都是采用RISC架構(gòu)進(jìn)行設(shè)計(jì)的。但是,在RISC處理器經(jīng)典的五級(jí)流水線結(jié)構(gòu)中,執(zhí)行階段存在的邏輯眾多,可能會(huì)產(chǎn)生擁堵現(xiàn)象,從而影響流水線的執(zhí)行速率。為了避免邏輯擁堵現(xiàn)象的發(fā)生,進(jìn)一步提高流水線的數(shù)據(jù)處理速度及擴(kuò)展處理器功能,本文對處理器的流水線結(jié)構(gòu)重新進(jìn)行劃分,提出了一種由指令取出單元(IF)、指令譯碼單元(ID)、控制邏輯執(zhí)行單元(FLE)、運(yùn)算單元(AU)和寄存器組(REF)五部分組成的新型五級(jí)流水線結(jié)構(gòu)。其中,在流水線的運(yùn)算單元添加了新型的乘累加器來拓展RISC處理器的功能,與普通乘累加器相比,此新型乘累加器注重電路結(jié)構(gòu)的簡化,并且其執(zhí)行速度提升了三倍。本論文研究了流水線結(jié)構(gòu)引入的結(jié)構(gòu)相關(guān)、數(shù)據(jù)相關(guān)和控制相關(guān)問題,并使用哈佛結(jié)構(gòu)、數(shù)據(jù)前推技術(shù)以及軟件編程的方法分別解決了這三種相關(guān)性問題。在新型流水線結(jié)構(gòu)的具體實(shí)現(xiàn)時(shí)使用Verilog HDL完成了流水線的邏輯設(shè)計(jì),利用Modelsim軟件對流水線各級(jí)以及整體結(jié)構(gòu)進(jìn)行了功能仿真,然后使用Quartus Ⅱ軟件對處理器進(jìn)行了邏輯綜合以及靜態(tài)時(shí)序分析。從仿真綜合的結(jié)果可以看出：處理器可以平穩(wěn)快速地執(zhí)行,并且流水線中的每一條指令都可以在一個(gè)時(shí)鐘周期內(nèi)執(zhí)行完畢。時(shí)序報(bào)告顯示：該處理器沒有發(fā)生任何時(shí)序違規(guī)現(xiàn)象,滿足時(shí)序設(shè)計(jì)要求,并且流水線結(jié)構(gòu)的最大工作頻率可以達(dá)到172.95MHz,與同類設(shè)計(jì)相比,提高了15.2%。最后,在FPGA實(shí)驗(yàn)板上對其進(jìn)行硬件調(diào)試,達(dá)到了本設(shè)計(jì)預(yù)期的目標(biāo)。
[Abstract]:Reduced instruction set computer (Reduced Instruction Set Computer, RISC) is an advanced processor design idea proposed in 1979. Its characteristic is to select the most frequently-used instruction in the processor, to fix the format of instruction and to reduce the addressing mode of instruction. Because of the advantages of simple and efficient RISC, it has been widely concerned by the industry after it was put forward. At present, 90% of processors in high performance server and embedded field are designed with RISC architecture. However, in the classical five-stage pipelined architecture of RISC processor, there is a lot of logic in the execution phase, which may result in congestion, which will affect the execution rate of the pipeline. In order to avoid the phenomenon of logic congestion, further improve the data processing speed of pipeline and extend the processor function, the pipeline structure of the processor is redivided in this paper. A novel five-stage pipeline structure is proposed, which consists of five parts: the instruction extraction unit (IF), the instruction decoding unit (ID), the (ID), control logic execution unit (AU), and the register group (REF) (REF). Among them, a new multiplicative accumulator is added to the pipeline unit to expand the function of RISC processor. Compared with the ordinary multiplier accumulator, the new multiplier accumulator emphasizes the simplification of the circuit structure, and its execution speed is three times higher than that of the common multiplier accumulator. In this paper, the structural correlation, data correlation and control related problems introduced by pipeline structure are studied, and the three correlation problems are solved by using Harvard structure, data forward technology and software programming. In the realization of the new pipeline structure, Verilog HDL is used to complete the logical design of the pipeline, and the functions of the pipeline at all levels and the whole structure are simulated by using the Modelsim software. Then, the logic synthesis and static timing analysis of the processor are carried out by using Quartus 鈪，

本文編號(hào)：2223249