【摘要】：隨著集成電路技術(shù)的快速發(fā)展,芯片集成的密度越來越高,微處理器的浮點運算能力已成為繼頻率后評價CPU性能的又一重要指標。在設(shè)計中通常使用專用部件來做浮點運算,即浮點運算單元(FPU),已逐漸成為現(xiàn)代處理器設(shè)計中的必不可少的組成部分。國內(nèi)外市場上的各種通用處理器幾乎都集成有浮點運算單元,但處理精度大多只包括32位單精度和64位雙精度,精度并不能滿足在高精度計算、圖形加速、數(shù)字信號處理等領(lǐng)域的應(yīng)用。除法和開方是浮點基本運算中比較復(fù)雜的運算,在設(shè)計中通常采用迭代乘的方法實現(xiàn),而查找表和乘法器寬度會對浮點運算性能有較大的影響。因此,設(shè)計高精度高性能的浮點除法、開方單元具有重要的理論價值和實用意義。 本文首先對Intel及AMD等浮點協(xié)處理器和浮點格式進行了分析,詳細研究了IEEE-754標準中規(guī)定的浮點格式,分析了浮點除法、開方運算依賴的數(shù)學(xué)原理及公式,并深入研究了基于牛頓迭代的Goldschmidt算法。對影響浮點運算性能的查找表設(shè)計和迭代乘法器寬度做了深入探討,經(jīng)過分析研究本文設(shè)計采用多表相加的倒數(shù)表構(gòu)造方法和75×75乘法器。之后,詳細描述了除法／開方運算單元的整體設(shè)計和實現(xiàn)細節(jié)。經(jīng)驗證,本文所設(shè)計的除法／開方單元可完成高精度的除法和開方運算,且運算周期較短,同時支持32位單精度、64位雙精度和80位擴展精度三種不同的浮點格式。最后,設(shè)計的運算單元采用ASIC全定制的電路設(shè)計方法,并使用SMIC0.13微米的工藝庫進行了綜合仿真驗證,其工作主頻和性能均達到了設(shè)計要求,已流片并應(yīng)用于某領(lǐng)域。
[Abstract]:With the rapid development of integrated circuit technology, the density of chip integration becomes higher and higher. The floating-point computing ability of microprocessor has become another important index to evaluate the performance of CPU after frequency. In design, special components are usually used to do floating-point operation, that is, floating-point operation unit (FPU),) has gradually become an indispensable part in modern processor design. Almost all kinds of universal processors at home and abroad integrate floating-point operation units, but the processing accuracy includes only 32-bit single precision and 64-bit double-precision, so the precision can not be satisfied in high-precision calculation and graphics acceleration. The application of digital signal processing and other fields. Division and square are complex operations in the basic operation of floating-point. Iterative multiplication is usually used in the design, and the width of lookup table and multiplier has great influence on the performance of floating-point operation. Therefore, it is of great theoretical value and practical significance to design floating-point division with high precision and high performance. In this paper, the floating-point coprocessor and floating-point format such as Intel and AMD are analyzed, the floating-point format specified in IEEE-754 standard is studied in detail, and the mathematical principle and formula of floating-point division and square dependence are analyzed. The Goldschmidt algorithm based on Newton iteration is studied in detail. The design of look-up table and the width of iterative multiplier, which affect the performance of floating-point operation, are discussed in depth. The reciprocal table construction method and 75 脳 75 multiplier are designed and analyzed in this paper. After that, the whole design and implementation of division / square operation unit are described in detail. It is proved that the division / square unit designed in this paper can accomplish high precision division and square operation, and the operation period is shorter. At the same time, it supports three different floating-point schemes with 32-bit single precision and 64-bit double-precision and 80-bit extended precision. Finally, the operation unit is designed by using the ASIC fully customized circuit design method, and the comprehensive simulation is carried out by using the SMIC0.13 micron process library. Its main frequency and performance meet the design requirements, and the flow sheet has been applied to a certain field.
【學(xué)位授予單位】：華北電力大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP332

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