高性能SDRAM控制器設(shè)計(jì)及軟硬件結(jié)合測(cè)試
發(fā)布時(shí)間：2018-08-28 19:58
【摘要】：隨著通信、多媒體技術(shù)的發(fā)展，嵌入式片上系統(tǒng)(SoC：System on Chip)的應(yīng)用范圍越來(lái)越廣泛，性能要求也越來(lái)越高。嵌入式SoC的性能主要取決于嵌入式SoC內(nèi)核的處理能力和存儲(chǔ)器的帶寬，而在SoC內(nèi)核性能越來(lái)越高的情況下，存儲(chǔ)器帶寬成為了SoC整體性能提升的瓶頸。SDRAM憑借其快速、穩(wěn)定、功耗低、支持猝發(fā)式（burst）讀寫等眾多優(yōu)良特性，成為了當(dāng)今SoC外部緩存的首選。因此，，研究設(shè)計(jì)高性能SDRAM控制器有著重要的意義。 本文針對(duì)SoC芯片架構(gòu)設(shè)計(jì)一款高性能SDR/DDR SDRAM控制器，通過(guò)軟件測(cè)試優(yōu)化性能，并在Xilinx Virtex-4XC4VLX200FPGA中實(shí)現(xiàn)。 本文首先介紹SDRAM存儲(chǔ)器的基本工作原理，給出了SDRAM支持的指令和典型的操作時(shí)序，按照J(rèn)EDEC SDRAM規(guī)范制定了詳細(xì)的SDRAM控制器設(shè)計(jì)方案，并重點(diǎn)介紹了主要模塊的設(shè)計(jì)方法。同時(shí)，本文介紹并比較幾種常用的總線和仲裁方式，在SDRAM控制器中植入能保證帶寬和讀寫延時(shí)的總線仲裁方式。 其次，參考典型的SDRAM存儲(chǔ)器優(yōu)化方法，在現(xiàn)有的SoC芯片架構(gòu)下優(yōu)化控制器。采用的優(yōu)化方式包括：基于QoS優(yōu)化多端口仲裁方式；分散刷新操作并盡可能在SDRAM處于空閑狀態(tài)時(shí)進(jìn)行刷新；改進(jìn)映射方法來(lái)充分利用SDRAM的行緩沖區(qū)等。 最后，將該控制器集成到SoC仿真平臺(tái)中，使用Cadence公司的NCVerilog對(duì)其進(jìn)行仿真，分析優(yōu)化結(jié)果。同時(shí)建立相應(yīng)FPGA原型。 仿真和FPGA驗(yàn)證的結(jié)果表明：控制器達(dá)到了預(yù)定的設(shè)計(jì)指標(biāo)，能夠兼容多種規(guī)格的SDRAM，包括SDR、DDR�；诨鶞�(zhǔn)程序STREAM和直接存儲(chǔ)器存�。―MA）的評(píng)估結(jié)果表明：SDRAM控制器優(yōu)化后，系統(tǒng)存儲(chǔ)器帶寬提高了17.8％、性能指標(biāo)提高了30.6％。
[Abstract]:With the development of communication and multimedia technology, embedded on-chip system (SoC:System on Chip) is applied more and more widely. The performance of embedded SoC mainly depends on the processing ability of embedded SoC kernel and the bandwidth of memory. However, with the increasing performance of SoC kernel, memory bandwidth has become the bottleneck of overall performance improvement of SoC. Low power consumption, support burst (burst) reading and writing, and many other excellent features, has become the first choice of SoC external cache. Therefore, it is of great significance to study and design high performance SDRAM controller. In this paper, a high performance SDR/DDR SDRAM controller is designed for SoC chip architecture. The performance is optimized by software test and implemented in Xilinx Virtex-4XC4VLX200FPGA. In this paper, the basic working principle of SDRAM memory is introduced, the instruction supported by SDRAM and the typical operation timing are given, the detailed design scheme of SDRAM controller is made according to JEDEC SDRAM specification, and the design method of main modules is introduced emphatically. At the same time, several common bus and arbitration methods are introduced and compared in this paper. The bus arbitration method which can guarantee bandwidth and read / write delay is embedded in the SDRAM controller. Secondly, referring to the typical SDRAM memory optimization method, the controller is optimized under the existing SoC chip architecture. The optimization methods adopted include: optimizing multi-port arbitration mode based on QoS; decentralized refresh operation and refresh when SDRAM is in idle state as far as possible; improving mapping method to make full use of SDRAM row buffer and so on. Finally, the controller is integrated into the SoC simulation platform, and the NCVerilog of Cadence is used to simulate the controller, and the optimization results are analyzed. At the same time, build the corresponding FPGA prototype. The results of simulation and FPGA verification show that the controller has reached the predetermined design target and can be compatible with various specifications of SDRAM, including SDR,DDR.. The evaluation results based on reference program STREAM and direct memory access (DMA) show that the memory bandwidth of the system is increased by 17.8and the performance index is improved by 30.6after the controller is optimized.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333
本文編號(hào)：2210455
[Abstract]:With the development of communication and multimedia technology, embedded on-chip system (SoC:System on Chip) is applied more and more widely. The performance of embedded SoC mainly depends on the processing ability of embedded SoC kernel and the bandwidth of memory. However, with the increasing performance of SoC kernel, memory bandwidth has become the bottleneck of overall performance improvement of SoC. Low power consumption, support burst (burst) reading and writing, and many other excellent features, has become the first choice of SoC external cache. Therefore, it is of great significance to study and design high performance SDRAM controller. In this paper, a high performance SDR/DDR SDRAM controller is designed for SoC chip architecture. The performance is optimized by software test and implemented in Xilinx Virtex-4XC4VLX200FPGA. In this paper, the basic working principle of SDRAM memory is introduced, the instruction supported by SDRAM and the typical operation timing are given, the detailed design scheme of SDRAM controller is made according to JEDEC SDRAM specification, and the design method of main modules is introduced emphatically. At the same time, several common bus and arbitration methods are introduced and compared in this paper. The bus arbitration method which can guarantee bandwidth and read / write delay is embedded in the SDRAM controller. Secondly, referring to the typical SDRAM memory optimization method, the controller is optimized under the existing SoC chip architecture. The optimization methods adopted include: optimizing multi-port arbitration mode based on QoS; decentralized refresh operation and refresh when SDRAM is in idle state as far as possible; improving mapping method to make full use of SDRAM row buffer and so on. Finally, the controller is integrated into the SoC simulation platform, and the NCVerilog of Cadence is used to simulate the controller, and the optimization results are analyzed. At the same time, build the corresponding FPGA prototype. The results of simulation and FPGA verification show that the controller has reached the predetermined design target and can be compatible with various specifications of SDRAM, including SDR,DDR.. The evaluation results based on reference program STREAM and direct memory access (DMA) show that the memory bandwidth of the system is increased by 17.8and the performance index is improved by 30.6after the controller is optimized.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP333
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