【摘要】：近年來,處理器的能耗問題日益突出,單處理器到多核處理器,雖然在性能上有所提高,但同時(shí)導(dǎo)致了更多的能量消耗,不僅引發(fā)了難以解決的散熱問題,還導(dǎo)致系統(tǒng)的可靠性下降。因此,在滿足時(shí)間約束條件下,如何盡可能的降低系統(tǒng)能耗,已經(jīng)成為多核處理器實(shí)時(shí)節(jié)能調(diào)度領(lǐng)域的研究熱點(diǎn)。 已有算法的研究重點(diǎn)在于如何充分利用任務(wù)的實(shí)際執(zhí)行時(shí)間α,遠(yuǎn)小于最壞情況執(zhí)行時(shí)間ωi所產(chǎn)生的動(dòng)態(tài)空閑時(shí)間以及任務(wù)在時(shí)限之前完成而產(chǎn)生的靜態(tài)空閑時(shí)間,設(shè)計(jì)速率調(diào)度算法來合理降低處理器核電壓/頻率,達(dá)到同時(shí)滿足硬實(shí)時(shí)任務(wù)時(shí)限約束與最少能耗的統(tǒng)一目標(biāo)。本文在利用空閑時(shí)間降低速率的同時(shí),盡量減少處理器切換電壓/頻率所造成的能耗。 本文的主要工作如下： (1)提出一種新的多核處理器節(jié)能調(diào)度算法,該方法基于空閑時(shí)間回收策略和盡量減少處理器頻率切換造成的能耗。首先獲得前面執(zhí)行任務(wù)的平均任務(wù)執(zhí)行比率,來估算下一個(gè)任務(wù)的執(zhí)行速率,從而將其映射到速率最相近的處理器上,以減少處理器改變速率時(shí)所消耗的能耗。并通過讓相鄰的兩個(gè)任務(wù)共享處理器上的空閑時(shí)間來降低處理器的執(zhí)行速率,從而達(dá)到減少能耗的目的。通過理論推導(dǎo)和分析,將新算法與近三年來的算法進(jìn)行對(duì)比測試,結(jié)果表明在大部分條件下,新算法能夠獲得更好的節(jié)能效果。 (2)根據(jù)大量測試數(shù)據(jù),深入分析了影響算法節(jié)能效率的因素以及算法的調(diào)度約束條件和算法的適用條件,進(jìn)而提出了三種改進(jìn)算法TR-SS2(負(fù)載均衡策略)、ESR-SS2-CE和ESR-SS2-M,增加對(duì)速度的約束條件,分別采用估算速度和最大速度來確定單處理器上的執(zhí)行速度。并將改進(jìn)算法與已有算法對(duì)比測試分析,結(jié)果表明改進(jìn)算法能夠取得更好的節(jié)能效果。
[Abstract]:In recent years, the problem of processor energy consumption has become increasingly prominent. Although the performance of single-processor to multi-core processor has been improved, it has also led to more energy consumption, which has not only led to the difficult problem of heat dissipation. It also reduces the reliability of the system. Therefore, how to reduce the system energy consumption as much as possible has become a hotspot in the field of real-time energy-saving scheduling of multi-core processors. The emphasis of the existing algorithms is how to make full use of the actual execution time 偽, which is far less than the dynamic idle time generated by the worst case execution time 蠅 I and the static idle time generated by the completion of the task before the time limit. A rate scheduling algorithm is designed to reasonably reduce the core voltage / frequency of the processor and achieve the goal of simultaneously satisfying the time limit of hard real-time task and the minimum energy consumption. In this paper, the energy consumption caused by switching voltage / frequency of processor is minimized while the idle time is used to reduce the rate. The main work of this paper is as follows: (1) A new multi-core processor energy-saving scheduling algorithm is proposed, which is based on idle time recovery strategy and minimizes the energy consumption caused by processor frequency switching. First, the average task execution ratio of the previous task is obtained to estimate the execution rate of the next task and map it to the processor with the most similar rate to reduce the energy consumption when the processor changes the rate. The idle time on the processor is shared by two adjacent tasks to reduce the execution rate of the processor, thus reducing the energy consumption. Through theoretical deduction and analysis, the new algorithm is compared with the algorithm in recent three years. The results show that under most conditions, the new algorithm can achieve better energy saving effect. (2) according to a large number of test data, The factors that affect the efficiency of the algorithm, the scheduling constraints of the algorithm and the applicable conditions of the algorithm are analyzed in depth. Then, three improved algorithms, TR-SS2 (load balancing strategy), ESR-SS2-CE and ESR-SS2-M, are proposed to increase the speed constraints. The estimated speed and the maximum speed are used to determine the execution speed on the single processor. The results show that the improved algorithm can achieve better energy saving effect.
【學(xué)位授予單位】：武漢理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP301.6;TP332

【引證文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 劉寶寧;基于多核平臺(tái)的實(shí)時(shí)混合任務(wù)調(diào)度算法研究[D];武漢理工大學(xué);2013年

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本文編號(hào)：2205749