一種嵌入式Flash存儲器的內(nèi)建自測試電路的設(shè)計
發(fā)布時間：2018-08-25 12:46
【摘要】：當今眾多SoC芯片都會使用FLASH存儲器,而且存儲器容量正在不斷增加,這給芯片的測試工作帶來很多困難。時至今日,業(yè)界已經(jīng)為測試嵌入式存儲器開發(fā)了很多算法。不過,由于FLASH存儲器的擦寫周期長,需要對一般的算法加以取舍和改進。本論文的撰寫背景是為華虹NEC公司EF130工藝的FLASH設(shè)計一套測試方法,決定采用內(nèi)建自測試(BIST)電路,可以根據(jù)測試要求選擇使用MSCAN算法、棋盤格算法、對角線算法。為了節(jié)省芯片引腳,采用串并轉(zhuǎn)換電路將串行輸入的測試信號轉(zhuǎn)成并行信號施加到待測電路。文章首先通過闡述芯片測試的原理來引出測試的一般方法,然后介紹存儲器測試的特點和故障模型；接下來闡述FLASH存儲器的擦寫機制,然后介紹一下被測試FLASH的特征；接著交代設(shè)計方案的制定過程和完成設(shè)計的具體方法,通過編寫verilog代碼來實現(xiàn)設(shè)計,最后仿真代碼,通過驗證。經(jīng)過芯片流片后測試,到達了預(yù)定的要求,verilog代碼以軟核形式已經(jīng)交付客戶使用。
[Abstract]:Nowadays, many SoC chips will use FLASH memory, and the memory capacity is increasing, which brings a lot of difficulties to the chip testing. Today, the industry has developed a lot of algorithms for testing embedded memory. However, due to the long writing period of FLASH memory, the general algorithm needs to be selected and improved. The background of this thesis is to design a set of test methods for FLASH of EF130 process of Huahong NEC Company. It is decided to adopt built-in self-test (BIST) circuit. According to the test requirements, we can choose MSCAN algorithm, checkerboard algorithm and diagonal algorithm. In order to save the chip pin, the serial input test signal is converted into a parallel signal to be applied to the circuit to be tested by serial parallel conversion circuit. This paper first introduces the principle of chip testing to lead to the general method of testing, then introduces the characteristics of memory testing and fault model, then describes the erasure mechanism of FLASH memory, and then introduces the characteristics of FLASH being tested. Then it explains the process of making the design scheme and the concrete method of completing the design, and realizes the design by writing the verilog code, finally simulates the code, and verifies it. After chip stream test, the required code has been delivered to customers in soft core form.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP333
本文編號：2202928
[Abstract]:Nowadays, many SoC chips will use FLASH memory, and the memory capacity is increasing, which brings a lot of difficulties to the chip testing. Today, the industry has developed a lot of algorithms for testing embedded memory. However, due to the long writing period of FLASH memory, the general algorithm needs to be selected and improved. The background of this thesis is to design a set of test methods for FLASH of EF130 process of Huahong NEC Company. It is decided to adopt built-in self-test (BIST) circuit. According to the test requirements, we can choose MSCAN algorithm, checkerboard algorithm and diagonal algorithm. In order to save the chip pin, the serial input test signal is converted into a parallel signal to be applied to the circuit to be tested by serial parallel conversion circuit. This paper first introduces the principle of chip testing to lead to the general method of testing, then introduces the characteristics of memory testing and fault model, then describes the erasure mechanism of FLASH memory, and then introduces the characteristics of FLASH being tested. Then it explains the process of making the design scheme and the concrete method of completing the design, and realizes the design by writing the verilog code, finally simulates the code, and verifies it. After chip stream test, the required code has been delivered to customers in soft core form.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TP333
【參考文獻】
相關(guān)期刊論文 前1條
1 孫華義;鄭學(xué)仁;閭曉晨;王頌輝;吳焯焰;;嵌入式存儲器內(nèi)建自測試的一種新型應(yīng)用[J];中國集成電路;2007年11期
，本文編號：2202928
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