【摘要】：隨著半導(dǎo)體集成電路的不斷發(fā)展,傳統(tǒng)的Flash存儲器的發(fā)展遭遇了瓶頸�；诩{米晶粒的浮柵存儲器由于其分立電荷存儲的優(yōu)點受到越來越多的關(guān)注,而基于不同機制的新型阻變存儲器由于其高速的讀寫速度及其與當前CMOS相兼容的制備工藝近年來成為存儲器領(lǐng)域的研究熱點,如何利用現(xiàn)代的半導(dǎo)體工藝來提高這些存儲器的性能是目前科學(xué)界和產(chǎn)業(yè)界的重要研究課題。 本文針對一種納米硅浮柵存儲器結(jié)構(gòu)——poly-Si/Si3N4/nc-Si/SiO2MOS結(jié)構(gòu),研究了以Al電極為掩膜反應(yīng)離子刻蝕(RIE)多晶硅的工藝技術(shù),獲得了比較理想的刻蝕工藝條件,成功制備了獨立的poly-Si/Si3N4/nc-Si/SiO2MOS單元。為了改進阻變納米硅存儲器的電學(xué)特性,我們采用納米球RIE工藝制備了納米硅陣列,在阻變納米硅存儲器中實現(xiàn)了對硅量子點的空間分布的限制。在此基礎(chǔ)上我們進一步利用高精度的光刻工藝來減小阻變納米硅存儲器頂電極面積以實現(xiàn)納米硅存儲器中電場分布的限制,以此優(yōu)化其阻變性能,發(fā)現(xiàn)隨著電極面積減小阻變納米硅存儲器的性能獲得了提高。 在成功獲得獨立poly-Si/Si3N4/nc-Si/SiO2MOS結(jié)構(gòu)單元的基礎(chǔ)上,對其電容、電導(dǎo)特性進行了測量,通過C-V曲線計算了nc-Si的密度,研究了納米硅在電荷存儲中所起的主要作用。發(fā)現(xiàn)了C-V曲線隨著頻率的增加沿著電壓的負方向偏移,并觀察到了G/ω-V曲線中電導(dǎo)峰隨頻率升高而偏移,基于對變頻C-V曲線和G/ω-V曲線隨隨頻率變化關(guān)系的詳細分析,證明了納米硅和界面態(tài)在電荷存儲中的共同作用。
[Abstract]:With the continuous development of semiconductor integrated circuits, the development of traditional Flash memory has encountered a bottleneck. Floating gate memory based on nanocrystalline has attracted more and more attention because of its advantages of discrete charge storage. In recent years, novel resistive memory based on different mechanisms has become a research hotspot in the field of memory due to its high speed of reading and writing and its compatibility with current CMOS. How to use modern semiconductor technology to improve the performance of these memories is an important research topic in science and industry. In this paper, a poly-Si / Si _ 3N _ 4 / nc-Si / Si _ 2O _ 2MOS structure is studied. The etching process of (RIE) polysilicon with Al electrode as the mask ion is studied. The ideal etching conditions are obtained, and the independent poly-Si/Si3N4/nc-Si/SiO2MOS cells are successfully fabricated. In order to improve the electrical properties of the resistive nanocrystalline silicon memory, a nanospheres RIE process was used to fabricate the nanocrystalline silicon arrays, which limited the spatial distribution of the silicon quantum dots in the resistive nanocrystalline silicon memory. On this basis, we further use high-precision lithography to reduce the area of the top electrode of the resistive nanocrystalline silicon memory so as to limit the electric field distribution in the nano-silicon memory and optimize its resistance performance. It is found that with the decrease of electrode area, the performance of nano silicon memory is improved. On the basis of successfully obtaining the independent poly-Si/Si3N4/nc-Si/SiO2MOS structure unit, the capacitance and conductance characteristics are measured, the density of nc-Si is calculated by C-V curve, and the main role of nano-silicon in charge storage is studied. It is found that the C-V curve shifts along the negative direction of the voltage with the increase of frequency, and the conductivity peak in the G / 蠅 -V curve is offset with the increase of the frequency. Based on the detailed analysis of the relationship between the frequency variation of the frequency conversion C-V curve and the G / 蠅 -V curve, The interaction of nano-silicon and interfacial states in charge storage is proved.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP333

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