【摘要】：航空設備系統(tǒng)之間的通信十分復雜和多樣，且需要不同的硬件接口來滿足不同的航空設備，隨著作戰(zhàn)信息數(shù)據(jù)總量的增加，和數(shù)字技術的進步，為了簡化這一狀況，就提出了數(shù)據(jù)總線，以減少系統(tǒng)的布線重量，大大提高系統(tǒng)的可靠性。 MIL-STD-1553B總線是美國定義的一種軍用串行總線標準，其中的技術要求有：規(guī)定了數(shù)字式時分制指令"響應型多路傳輸數(shù)據(jù)總線以及接口電子設備，，而且規(guī)定了多路傳輸數(shù)據(jù)總線的工作原理和總線上的信息流及要采用的電氣和功能格式。數(shù)據(jù)傳輸方式是屏蔽雙絞線方式，信號傳輸形式是串行數(shù)字脈沖的方式，數(shù)據(jù)代碼形式為雙相曼徹斯特碼。 本文由具體工程項目入手，設計了一款基于MIL-STD-1553B通信協(xié)議的總線模塊，對協(xié)議處理器芯片和收發(fā)器芯片分別作了深入研究。協(xié)議處理器芯片中總線控制器、遠程終端和總線監(jiān)視器是典型的數(shù)字集成電路，收發(fā)器則采用數(shù)�；旌想娐穪韺崿F(xiàn)。文章開始介紹了MIL-STD-1553B總線協(xié)議的主要內(nèi)容，集中討論了總線特性、硬件設備和協(xié)議。這些內(nèi)容對1553B總線模塊的各個參數(shù)提供了設計標準，直接決定了總線模塊設計所要達到的各項指標。然后，分別對總線協(xié)議處理器和總線收發(fā)器進行了設計，描述了電路總體結構，明確了電路所起到的作用，主要對收發(fā)器部分包括發(fā)送器、接收器、基準電路、控制電路等進行詳細設計。最后利用Cadence，Hsim和Hspice對電路進行了仿真驗證，并給出各電路的仿真波形與1553B模塊的總體仿真結果。仿真結果表明，所設計的1553B總線模塊達到了協(xié)議的功能和可靠性要求。
[Abstract]:The communication between aeronautical equipment systems is very complex and diverse, and different hardware interfaces are needed to satisfy different aviation equipments. With the increase of the total amount of battle information data and the progress of digital technology, to simplify this situation, A data bus is proposed to reduce the weight of the system wiring and greatly improve the reliability of the system. MIL-STD-1553B bus is a military serial bus standard defined by the United States. The technical requirements are as follows: the digital time division instruction "responsive multiplexing data bus and interface electronic equipment" are stipulated. The working principle of the multiplex data bus, the information flow on the bus and the electric and functional format to be adopted are also specified. Data transmission mode is shielded twisted-pair wire, signal transmission mode is serial digital pulse mode, data code form is dual-phase Manchester code. In this paper, a bus module based on MIL-STD-1553B communication protocol is designed, and the protocol processor chip and transceiver chip are studied in detail. The bus controller, remote terminal and bus monitor are typical digital integrated circuits in protocol processor chip, and the transceiver is realized by mixed digital-analog circuit. In this paper, the main contents of MIL-STD-1553B bus protocol are introduced, and the bus characteristics, hardware devices and protocols are discussed. These contents provide the design standard for each parameter of the 1553B bus module and directly determine the various indexes to be achieved in the design of the bus module. Then, the bus protocol processor and bus transceiver are designed, the overall structure of the circuit is described, and the function of the circuit is clarified. The transceiver includes transmitter, receiver and reference circuit. The control circuit is designed in detail. Finally, the circuit is simulated by Hspice and Hsim, and the simulation waveform of each circuit and the overall simulation results of 1553B module are given. Simulation results show that the designed 1553B bus module meets the function and reliability requirements of the protocol.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP336

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本文編號：2192290