一種新的大容量SRAM編譯器設(shè)計(jì)
發(fā)布時(shí)間：2018-08-12 10:15
【摘要】：介紹了一種大容量的SRAM編譯器設(shè)計(jì)技術(shù)。根據(jù)SRAM容量和結(jié)構(gòu),提出了新的建模方案,并建立更優(yōu)化的時(shí)序和功耗模型。同時(shí),根據(jù)大容量SRAM在面積和性能上的需求,選擇不同的譯碼器和拼接結(jié)構(gòu),采用合適的IP核進(jìn)行拼接,并從結(jié)構(gòu)上實(shí)現(xiàn)。對(duì)512kb和1 Mb的SRAM進(jìn)行了流片測(cè)試,測(cè)試結(jié)果表明,該方案對(duì)于大容量的SRAM編譯器設(shè)計(jì)是有效的。
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者單位】： 中國(guó)科學(xué)技術(shù)大學(xué)工程科學(xué)學(xué)院;
【基金】：國(guó)家自然科學(xué)基金資助項(xiàng)目(61474001)
【分類號(hào)】：TP333;TP314
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者單位】： 中國(guó)科學(xué)技術(shù)大學(xué)工程科學(xué)學(xué)院;
【基金】：國(guó)家自然科學(xué)基金資助項(xiàng)目(61474001)
【分類號(hào)】：TP333;TP314
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2 王繼軍;;圖像插值空間大容量可逆數(shù)字水印算法[J];中國(guó)圖象圖形學(xué)報(bào);2014年04期
3 程v灹，
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