發(fā)布時(shí)間：2018-08-11 17:03

【摘要】：近年來，智能音頻應(yīng)用的普及對手持設(shè)備的計(jì)算能力的要求越來越高，然而手持設(shè)備的續(xù)航時(shí)間卻越來越短。更高的性能，更低的功耗，是移動處理器的主要發(fā)展方向。多核憑借其強(qiáng)大的處理能力與相對較為合理的功耗、散熱、制造成本成為了移動處理器的主流方案。 APC（Audio Processing Core）是面向音頻應(yīng)用優(yōu)化設(shè)計(jì)的低功耗DSP，采用多核設(shè)計(jì)，具有計(jì)算資源受限、多級混合型存儲架構(gòu)以及無操作系統(tǒng)環(huán)境等特點(diǎn)。 音頻應(yīng)用必須經(jīng)過并行化才能發(fā)揮多核APC的計(jì)算能力。并行程序需要通過并行編程模型來編寫�，F(xiàn)有的并行編程模型各自適合特定架構(gòu)。APC也需要一套對其硬件架構(gòu)優(yōu)化的并行程模型。 本文為多核APC設(shè)計(jì)并實(shí)現(xiàn)了一套并行編程模型。該并行編程模型具有輕量級的運(yùn)行時(shí)環(huán)境，支持多級混合型存儲架構(gòu)，支持多種核間交互方式。 為了評估文中并行編程模型的性能以及開銷，設(shè)計(jì)并實(shí)現(xiàn)了一個(gè)APC多核指令集模擬器，模擬并行程序運(yùn)行所需的硬件環(huán)境。 將四個(gè)實(shí)驗(yàn)用例移植到多核指令集模擬器上，實(shí)驗(yàn)結(jié)果表明，，文中的并行編程環(huán)境以較小的開銷、簡潔易用的編程接口發(fā)揮出了多核APC的計(jì)算能力。該并行環(huán)境的設(shè)計(jì)實(shí)現(xiàn)過程，對面向特定應(yīng)用的低功耗DSP的并行編程環(huán)境設(shè)計(jì)具有一定的參考意義。
[Abstract]:In recent years, the popularity of intelligent audio applications requires more and more computing power of handheld devices, but the lifetime of handheld devices is becoming shorter and shorter. Higher performance and lower power consumption are the main development directions of mobile processors. With its powerful processing power and relatively reasonable power consumption, heat dissipation and manufacturing cost, multicore has become the mainstream solution of mobile processor,. APC (Audio Processing Core) is a low-power DSPs for the optimization design of audio applications, and adopts multi-core design. It has the characteristics of limited computing resources, multilevel hybrid storage architecture and no operating system environment. Audio applications must be parallelized to achieve multi-core APC computing power. Parallel programs need to be written in parallel programming models. The existing parallel programming models are suitable for specific architectures. APC also needs a set of parallel stroke models to optimize its hardware architecture. This paper designs and implements a parallel programming model for multi-core APC. The parallel programming model has a lightweight runtime environment, supports a multi-level hybrid storage architecture, and supports a variety of intercore interactions. In order to evaluate the performance and overhead of the parallel programming model in this paper, a APC multi-core instruction set simulator is designed and implemented to simulate the hardware environment required for parallel program running. Four experiment cases are transplanted to the multi-core instruction set simulator. The experimental results show that the parallel programming environment in this paper exerts the computing power of multi-core APC with small overhead and simple and easy-to-use programming interface. The design and implementation process of this parallel environment has certain reference significance for the design of low power DSP parallel programming environment for specific applications.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TP311.11

【參考文獻(xiàn)】

相關(guān)期刊論文 前3條

1 王昌林;張勇;李東生;;CMOS集成電路功耗分析及其優(yōu)化方法[J];艦船電子工程;2006年03期

2 陶峰峰,付宇卓;DSP指令集仿真器的設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)仿真;2005年09期

3 李晉,葛敬國;Linux下互斥機(jī)制及其分析[J];計(jì)算機(jī)應(yīng)用研究;2005年08期

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