【摘要】：在嵌入式移動(dòng)設(shè)備中應(yīng)用多媒體技術(shù),需要同時(shí)考慮性能、成本、功耗以及靈活性等諸多方面的因素,帶有媒體擴(kuò)展單元的嵌入式處理器作為其中一種較為平衡的解決方案,得到了廣泛的關(guān)注與研究。本論文以此為背景,在研究多種媒體運(yùn)算以及典型擴(kuò)展指令集的基礎(chǔ)上,對嵌入式處理器中的媒體加速單元進(jìn)行設(shè)計(jì)并實(shí)現(xiàn)一種新型去隔行算法,現(xiàn)將本論文的主要研究工作與創(chuàng)新點(diǎn)歸納如下： 1.對多種媒體運(yùn)算與擴(kuò)展指令集的研究。論文針對多媒體應(yīng)用中兩大重要的技術(shù)——音視頻編解碼和后處理技術(shù)進(jìn)行展開,分別對MPEG2、MPEG4、H.264和圖像縮放、視頻去隔行、幀頻提升進(jìn)行算法研究、運(yùn)算提取以及實(shí)驗(yàn)分析,同時(shí)借鑒主流的多媒體擴(kuò)展指令集,結(jié)合現(xiàn)有處理器和指令集的特點(diǎn),根據(jù)Amdah1定律等影響處理器性能的因素,對媒體擴(kuò)展指令集進(jìn)行設(shè)計(jì),本文重點(diǎn)對SIMD加減、乘法及其相關(guān)的SAD、乘累加指令進(jìn)行研究。 2.多媒體加速單元的設(shè)計(jì)。在綜合考慮已有處理器機(jī)制的基礎(chǔ)上,多媒體加速單元整體采用亂序執(zhí)行和流水線平衡劃分的策略。通過采用成熟的乘法器IP,提升了設(shè)計(jì)的可靠性；通過將高位寬乘法運(yùn)算分解為并行的低位寬乘法運(yùn)算,縮短了組合邏輯的延時(shí)；通過內(nèi)部的重排序機(jī)制,保證了精確的中斷和異常處理；通過門控時(shí)鐘和操作數(shù)隔離的技術(shù),有效控制了功耗。 3.去隔行的多媒體應(yīng)用研究。本文提出了一種新型的基于運(yùn)動(dòng)分類的自適應(yīng)去隔行算法,創(chuàng)新性地引入了運(yùn)動(dòng)等級分類、維納中值濾波以及三重中值濾波,仿真實(shí)驗(yàn)表明,算法具有一定的先進(jìn)性。同時(shí),采用媒體處理器加以實(shí)現(xiàn),將其中復(fù)雜的運(yùn)算與媒體指令集進(jìn)行映射,并將其處理結(jié)果與算法仿真結(jié)果進(jìn)行對比分析。
[Abstract]:The application of multimedia technology in embedded mobile devices requires consideration of performance, cost, power consumption, flexibility and many other factors. Embedded processors with media expansion units are considered as one of the more balanced solutions. It has received extensive attention and research. Based on the research of various media operations and typical extended instruction sets, this paper designs the media acceleration unit in embedded processor and implements a new de-interlacing algorithm. The main research work and innovation of this paper are summarized as follows: 1. Research on multiple media operations and extended instruction sets. In this paper, two important technologies in multimedia applications, audio and video coding, decoding and post-processing, are developed. The algorithms, arithmetic extraction and experimental analysis of MPEG2 / MPEG4 / H.264 and image scaling, video de-interlacing, frame rate promotion are studied, respectively. At the same time, referring to the mainstream multimedia extended instruction set, combining the characteristics of the existing processor and instruction set, according to the factors that affect the processor performance, such as Amdah1's law, the media extended instruction set is designed. The emphasis of this paper is on the addition and subtraction of SIMD. Multiplication and related SAD, multiplicative cumulative instruction to study. 2. The design of multimedia acceleration unit. On the basis of synthetically considering the existing processor mechanism, the multimedia accelerating unit adopts the strategy of disorderly execution and pipeline balanced partitioning. By using mature multiplier IPs, the reliability of the design is improved. By decomposing the high bit width multiplication into parallel low width multiplication, the delay of combinational logic is shortened, and the internal reordering mechanism is used. Accurate interrupt and exception handling are ensured, and the power consumption is effectively controlled by the gated clock and Operand isolation technology. Research on Deinterlaced Multimedia applications. In this paper, a new adaptive de-interlacing algorithm based on motion classification is proposed, which innovatively introduces motion classification, Wiener median filter and triple median filter. The simulation results show that the algorithm is advanced to some extent. At the same time, the complex operation is mapped to the media instruction set by the media processor, and the processing results are compared with the simulation results of the algorithm.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP368.1;TP332

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本文編號：2160753