【摘要】：近年來(lái),支持高速短距離數(shù)據(jù)傳輸?shù)臒o(wú)線(xiàn)個(gè)人局域網(wǎng)(WPAN)技術(shù)得到了迅速的發(fā)展。IEEE802.15.3c標(biāo)準(zhǔn)定義了60GHz頻段的無(wú)線(xiàn)通信系統(tǒng)物理層(PHY),吏無(wú)線(xiàn)數(shù)據(jù)傳輸速率達(dá)到了2Gbps。從兆比特過(guò)渡到gigabit將給通信應(yīng)用領(lǐng)域帶來(lái)一次質(zhì)的飛躍,可以預(yù)見(jiàn)60GHz無(wú)線(xiàn)通信技術(shù)的應(yīng)用將對(duì)未來(lái)科技,經(jīng)濟(jì)和社會(huì)發(fā)展產(chǎn)生重要、重要的影響。 FFT處理器作為60GHz系統(tǒng)中的關(guān)鍵模塊,其決定了整個(gè)系統(tǒng)的性能。本文針對(duì)60GHz無(wú)線(xiàn)通信系統(tǒng)的要求,研究了一種高數(shù)據(jù)速率、低硬件復(fù)雜度的FFT處理器,取得成果如下： 1)根據(jù)512點(diǎn)FFT運(yùn)算的特點(diǎn),選擇基-25算法作為本文的實(shí)現(xiàn)算法。并對(duì)512點(diǎn)FFT運(yùn)算的旋轉(zhuǎn)因子分解方法進(jìn)行改進(jìn),簡(jiǎn)化其每一級(jí)運(yùn)算所需要的旋轉(zhuǎn)因子,從而使得復(fù)數(shù)乘法的個(gè)數(shù)相對(duì)傳統(tǒng)分解方法降低了20%： 2)分析并比較了多路延遲反饋(MDF, Multi-path delay-feedback)和多路延遲轉(zhuǎn)接(MDC, Multi-path delay commutator)兩種FFT處理器的硬件架構(gòu)的特點(diǎn),并根據(jù)60GHz系統(tǒng)對(duì)數(shù)據(jù)速率以及低硬件復(fù)雜度的要求,提出了一種性能與硬件消耗折衷的FFT處理器硬件實(shí)現(xiàn)方案。對(duì)整個(gè)FFT處理器進(jìn)行了系統(tǒng)級(jí)仿真,采用Verilog HDL對(duì)系統(tǒng)進(jìn)行RTL級(jí)描述并通過(guò)工具進(jìn)行邏輯綜合： 3)對(duì)高速FFT處理器測(cè)試方案進(jìn)行了研究。搭建了基于NIOSⅡ系統(tǒng)與UART串口的測(cè)試平臺(tái)。在A(yíng)ltera公司Stratix-Ⅲ FPGA芯片上對(duì)所設(shè)計(jì)的FFT處理器進(jìn)行了原型驗(yàn)證。其數(shù)據(jù)吞吐率可達(dá)到2.65GS/s@332MHz、信號(hào)與量化噪聲比(SQNR)為33.2db、消耗了7560LEs(Logical element)的硬件資源、完成512點(diǎn)運(yùn)算需要210ns (70cycles)。符合IEEE802.15.3c協(xié)議的要求。
[Abstract]:In recent years, the wireless personal area network (WPAN) technology, which supports high-speed and short-range data transmission, has been rapidly developed. IEEE 802.15.3c standard defines the physical layer of wireless communication system in 60GHz band and the wireless data transmission rate of (PHY), officials reaches 2Gbps. The transition from megabit to gigabit will bring a qualitative leap in the field of communication applications. It can be predicted that the application of 60GHz wireless communication technology will be important to the future development of science and technology, economy and society. As a key module in 60GHz system, FFT processor determines the performance of the whole system. According to the requirements of 60GHz wireless communication system, a FFT processor with high data rate and low hardware complexity is studied in this paper. The results are as follows: 1) according to the characteristics of 512-point FFT operation, Base-25 algorithm is chosen as the implementation algorithm in this paper. The rotation factor decomposition method of 512-point FFT operation is improved to simplify the rotation factor required for each operation. Therefore, the number of complex multiplication is reduced by 20% compared with the traditional decomposition method. 2) the hardware architecture characteristics of MDF (Multi-path delay-feedback) and Multi-path delay commutator) (MDC, Multi-path delay commutator) are analyzed and compared. According to the requirements of 60GHz system for data rate and low hardware complexity, a compromise between performance and hardware consumption for FFT processor hardware implementation is proposed. The whole FFT processor is simulated at the system level. Verilog HDL is used to describe the system at RTL level and logic synthesis is carried out through tools. 3) the test scheme of high speed FFT processor is studied. A test platform based on NIOS 鈪，

本文編號(hào)：2143408