【摘要】：近年來,支持高速短距離數(shù)據(jù)傳輸?shù)臒o線個人局域網(WPAN)技術得到了迅速的發(fā)展。IEEE802.15.3c標準定義了60GHz頻段的無線通信系統(tǒng)物理層(PHY),吏無線數(shù)據(jù)傳輸速率達到了2Gbps。從兆比特過渡到gigabit將給通信應用領域帶來一次質的飛躍,可以預見60GHz無線通信技術的應用將對未來科技,經濟和社會發(fā)展產生重要、重要的影響。 FFT處理器作為60GHz系統(tǒng)中的關鍵模塊,其決定了整個系統(tǒng)的性能。本文針對60GHz無線通信系統(tǒng)的要求,研究了一種高數(shù)據(jù)速率、低硬件復雜度的FFT處理器,取得成果如下： 1)根據(jù)512點FFT運算的特點,選擇基-25算法作為本文的實現(xiàn)算法。并對512點FFT運算的旋轉因子分解方法進行改進,簡化其每一級運算所需要的旋轉因子,從而使得復數(shù)乘法的個數(shù)相對傳統(tǒng)分解方法降低了20%： 2)分析并比較了多路延遲反饋(MDF, Multi-path delay-feedback)和多路延遲轉接(MDC, Multi-path delay commutator)兩種FFT處理器的硬件架構的特點,并根據(jù)60GHz系統(tǒng)對數(shù)據(jù)速率以及低硬件復雜度的要求,提出了一種性能與硬件消耗折衷的FFT處理器硬件實現(xiàn)方案。對整個FFT處理器進行了系統(tǒng)級仿真,采用Verilog HDL對系統(tǒng)進行RTL級描述并通過工具進行邏輯綜合： 3)對高速FFT處理器測試方案進行了研究。搭建了基于NIOSⅡ系統(tǒng)與UART串口的測試平臺。在Altera公司Stratix-Ⅲ FPGA芯片上對所設計的FFT處理器進行了原型驗證。其數(shù)據(jù)吞吐率可達到2.65GS/s@332MHz、信號與量化噪聲比(SQNR)為33.2db、消耗了7560LEs(Logical element)的硬件資源、完成512點運算需要210ns (70cycles)。符合IEEE802.15.3c協(xié)議的要求。
[Abstract]:In recent years, the wireless personal area network (WPAN) technology, which supports high-speed and short-range data transmission, has been rapidly developed. IEEE 802.15.3c standard defines the physical layer of wireless communication system in 60GHz band and the wireless data transmission rate of (PHY), officials reaches 2Gbps. The transition from megabit to gigabit will bring a qualitative leap in the field of communication applications. It can be predicted that the application of 60GHz wireless communication technology will be important to the future development of science and technology, economy and society. As a key module in 60GHz system, FFT processor determines the performance of the whole system. According to the requirements of 60GHz wireless communication system, a FFT processor with high data rate and low hardware complexity is studied in this paper. The results are as follows: 1) according to the characteristics of 512-point FFT operation, Base-25 algorithm is chosen as the implementation algorithm in this paper. The rotation factor decomposition method of 512-point FFT operation is improved to simplify the rotation factor required for each operation. Therefore, the number of complex multiplication is reduced by 20% compared with the traditional decomposition method. 2) the hardware architecture characteristics of MDF (Multi-path delay-feedback) and Multi-path delay commutator) (MDC, Multi-path delay commutator) are analyzed and compared. According to the requirements of 60GHz system for data rate and low hardware complexity, a compromise between performance and hardware consumption for FFT processor hardware implementation is proposed. The whole FFT processor is simulated at the system level. Verilog HDL is used to describe the system at RTL level and logic synthesis is carried out through tools. 3) the test scheme of high speed FFT processor is studied. A test platform based on NIOS 鈪，

本文編號：2143408