基于嵌入式PC和CPLD的測試適配器設計與實現
發(fā)布時間：2018-07-15 07:37
【摘要】：嵌入式技術伴隨著微處理器的誕生和發(fā)展,與計算機、微電子、網絡和通信技術緊密結合。21世紀以來,高性能嵌入式系統(tǒng)的硬件核心是擁有32位Alpha/ARM/PowerPC/MIPS/x86等架構的SoC,其硬件平臺具有強大的指令(RISC或CISC)處理能力和豐富的片上資源,可以支持Linux、VxWorks、iOS、Android等復雜的操作系統(tǒng)。Linux有著良好的性能,在國內外的程序員中普及率非常高,可安裝在手機、平板電腦、路由器、臺式機、大型機和超級計算機等各種設備中�，F場可編程門陣列(FPGA)和復雜可編程邏輯器件(CPLD)主要應用于數據采集、接口邏輯、高性能數字信號處理領域等。特別是在混合電平環(huán)境里面,傳統(tǒng)的電平轉換器件實現接口會導致電路復雜性提高,利用FPGA/CPLD支持多電平共存的特性,可以大大簡化設計方案。 本文設計和實現了一種基于x86架構、Linux操作系統(tǒng)的嵌入式PC和CPLD的測試適配器,它通過RS232串口接收并解析測試平臺發(fā)出的測試命令,根據命令對PCI接口的數字圖像模塊(DIM)和總線接口模塊(BIM)進行測試。嵌入式PC通過GPIO口模擬SPI時序控制CPLD的I/O輸出,為被測模塊(UUT)提供正常工作的時序；嵌入式PC通過對PCI接口的雙口RAM的讀寫控制UUT的工作；測試平臺與UUT通過總線通信,實時記錄并判斷測試結果。
[Abstract]:Embedded technology is accompanied by the birth and development of microprocessors, closely combined with computers, microelectronics, network and communication technology in the.21 century. The core of the hardware of high performance embedded systems is SoC with 32 bits of Alpha/ARM/PowerPC/MIPS/x86 architecture, and its hardware platform has powerful instruction (RISC or CISC) processing capability and rich tablet A complex operating system that supports Linux, VxWorks, iOS, Android and other complex operating systems,.Linux has good performance and is very popular among domestic and foreign programmers. It can be installed in various devices such as mobile phones, tablets, routers, desktops, mainframes and supercomputers. Field programmable gate array (FPGA) and complex programmable logic Devices (CPLD) are mainly used in data acquisition, interface logic, high performance digital signal processing and so on. Especially in the mixed level environment, the traditional level converter interface will lead to the improvement of the complexity of the circuit. Using FPGA/CPLD to support the characteristics of multilevel coexistence, the design scheme can be greatly simplified.
This paper designs and implements a test adapter for embedded PC and CPLD based on x86 architecture and Linux operating system. It receives and parses test commands issued by the test platform through the RS232 serial port, and tests the PCI interface's digital image module (DIM) and the bus interface module (BIM) based on the command. The embedded PC is used to simulate SPI by GPIO port. The order controls the I/O output of CPLD and provides the time sequence for the normal work for the measured module (UUT); embedded PC controls the work of UUT by reading and writing the dual port RAM of the PCI interface; the test platform is communicating with UUT through the bus to record and judge the test results in real time.
【學位授予單位】：華東理工大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP368.12
[Abstract]:Embedded technology is accompanied by the birth and development of microprocessors, closely combined with computers, microelectronics, network and communication technology in the.21 century. The core of the hardware of high performance embedded systems is SoC with 32 bits of Alpha/ARM/PowerPC/MIPS/x86 architecture, and its hardware platform has powerful instruction (RISC or CISC) processing capability and rich tablet A complex operating system that supports Linux, VxWorks, iOS, Android and other complex operating systems,.Linux has good performance and is very popular among domestic and foreign programmers. It can be installed in various devices such as mobile phones, tablets, routers, desktops, mainframes and supercomputers. Field programmable gate array (FPGA) and complex programmable logic Devices (CPLD) are mainly used in data acquisition, interface logic, high performance digital signal processing and so on. Especially in the mixed level environment, the traditional level converter interface will lead to the improvement of the complexity of the circuit. Using FPGA/CPLD to support the characteristics of multilevel coexistence, the design scheme can be greatly simplified.
This paper designs and implements a test adapter for embedded PC and CPLD based on x86 architecture and Linux operating system. It receives and parses test commands issued by the test platform through the RS232 serial port, and tests the PCI interface's digital image module (DIM) and the bus interface module (BIM) based on the command. The embedded PC is used to simulate SPI by GPIO port. The order controls the I/O output of CPLD and provides the time sequence for the normal work for the measured module (UUT); embedded PC controls the work of UUT by reading and writing the dual port RAM of the PCI interface; the test platform is communicating with UUT through the bus to record and judge the test results in real time.
【學位授予單位】：華東理工大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP368.12
【參考文獻】
相關期刊論文 前10條
1 李海松;劉佑寶;;有效降低開關電源EMI的電路設計[J];北京理工大學學報;2009年02期
2 周雒維;孫鵬菊;杜雄;;數字控制DC-DC變換器的延時離散模型及影響分析[J];電機與控制學報;2010年05期
3 吳允平;李旺彪;蘇偉達;蔡聲鎮(zhèn);陳聰慧;劉華松;;一種嵌入式系統(tǒng)的看門狗電路設計[J];電子器件;2010年05期
4 張軍;FPGA與CPLD器件使用經驗談[J];測控技術;2001年12期
5 王維;郭婷;王s，
本文編號：2123342
本文鏈接：http://sikaile.net/kejilunwen/jisuanjikexuelunwen/2123342.html
