基于高性能網(wǎng)絡(luò)處理器的存儲控制模塊的設(shè)計與驗證
發(fā)布時間：2018-07-14 09:08
【摘要】：近年來,伴隨著網(wǎng)絡(luò)規(guī)模和接口速度的增長,以通用處理器或以ASIC專用芯片為基礎(chǔ)的傳統(tǒng)網(wǎng)絡(luò)設(shè)備無法在性能上達到線速處理協(xié)議的處理要求,另一方面,網(wǎng)絡(luò)通信協(xié)議及標準快速變化更新,用戶的需求不斷提高,這就需要數(shù)據(jù)通信產(chǎn)品升級換代速度加快,開發(fā)周期縮短。網(wǎng)絡(luò)處理器(Network Processor, NP)在這種背景下應(yīng)運而生,它的出現(xiàn)既解決了通用處理器的低性能,又具有優(yōu)于ASIC的高靈活性,能夠更好的適應(yīng)數(shù)據(jù)通信行業(yè)快速的發(fā)展。網(wǎng)絡(luò)處理器作為典型的片上多處理器系統(tǒng)(MPSoC),對存儲器的訪問頻率很高,因此對訪存也給予了更高的要求。 本文針對網(wǎng)絡(luò)處理器芯片的應(yīng)用需求,重點研究了網(wǎng)絡(luò)處理器內(nèi)部的存儲控制模塊,并對其實現(xiàn)的具體功能加以分析和驗證。針對多核共享存儲器造成的訪存壓力,存儲控制模塊的設(shè)計采用分層仲裁機制,將固定優(yōu)先級仲裁機制與改進的輪轉(zhuǎn)優(yōu)先級仲裁機制相結(jié)合,既充分考慮了優(yōu)先性,又保證了低優(yōu)先級指令隊列的公平性,更為分組讀寫提供了可能。接口模塊作為控制單元的核心組成部分,重點研究了模塊內(nèi)部采用的指令緩存結(jié)構(gòu),并通過指令預取、預譯碼,實現(xiàn)指令控制信息的流水線式輸出,提高了存儲總線的利用率。 驗證的主要任務(wù)是保證設(shè)計與功能描述相符合,本文研究了目前幾種主要的SoC驗證技術(shù),結(jié)合存儲控制模塊的功能特點,采用軟件仿真與FPGA板級驗證相結(jié)合的驗證策略對其進行功能驗證,搭建了驗證平臺,并且根據(jù)存儲控制模塊具體實現(xiàn)功能提出了相應(yīng)的驗證方案,使用Modelsim工具進行了功能仿真,并在FPGA平臺上完成了板級測試,結(jié)果證實了存儲控制模塊能夠完成多處理器對片外存儲器SSRAM的訪問。
[Abstract]:In recent years, with the growth of network scale and interface speed, traditional network devices based on universal processor or ASIC special chip can not meet the processing requirements of line-speed processing protocol in performance, on the other hand, Network communication protocols and standards are rapidly changing and updating, and the demand of users is increasing. Therefore, it is necessary to speed up the upgrading of data communication products and shorten the development period. Network processor (NP) emerges as the times require under this background. It not only solves the low performance of general purpose processor, but also has high flexibility than ASIC. It can better adapt to the rapid development of data communication industry. As a typical multiprocessor system (MPSoC), network processor has a high access frequency to memory. Aiming at the application requirement of network processor chip, this paper focuses on the memory control module in network processor, and analyzes and verifies its specific function. Aiming at the memory access pressure caused by multi-core shared memory, the design of storage control module adopts layered arbitration mechanism, which combines fixed priority arbitration mechanism with improved rotation priority arbitration mechanism, which fully considers priority. It also ensures the fairness of low priority instruction queue and provides the possibility of packet reading and writing. As the core part of the control unit, the interface module focuses on the instruction buffer structure used in the module, and realizes the pipelined output of the instruction control information through the instruction prefetching and decoding, and improves the utilization ratio of the storage bus. The main task of verification is to ensure that the design is consistent with the function description. In this paper, several main SoC verification techniques are studied, combined with the functional characteristics of the memory control module. Using the verification strategy of software simulation and FPGA board level verification, the verification platform is built, and the corresponding verification scheme is put forward according to the concrete function of the storage control module, and the function simulation is carried out with Modelsim tool. The results show that the memory control module can complete the multiprocessor access to the off-chip memory SSRAM.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333;TN47
本文編號：2121167
[Abstract]:In recent years, with the growth of network scale and interface speed, traditional network devices based on universal processor or ASIC special chip can not meet the processing requirements of line-speed processing protocol in performance, on the other hand, Network communication protocols and standards are rapidly changing and updating, and the demand of users is increasing. Therefore, it is necessary to speed up the upgrading of data communication products and shorten the development period. Network processor (NP) emerges as the times require under this background. It not only solves the low performance of general purpose processor, but also has high flexibility than ASIC. It can better adapt to the rapid development of data communication industry. As a typical multiprocessor system (MPSoC), network processor has a high access frequency to memory. Aiming at the application requirement of network processor chip, this paper focuses on the memory control module in network processor, and analyzes and verifies its specific function. Aiming at the memory access pressure caused by multi-core shared memory, the design of storage control module adopts layered arbitration mechanism, which combines fixed priority arbitration mechanism with improved rotation priority arbitration mechanism, which fully considers priority. It also ensures the fairness of low priority instruction queue and provides the possibility of packet reading and writing. As the core part of the control unit, the interface module focuses on the instruction buffer structure used in the module, and realizes the pipelined output of the instruction control information through the instruction prefetching and decoding, and improves the utilization ratio of the storage bus. The main task of verification is to ensure that the design is consistent with the function description. In this paper, several main SoC verification techniques are studied, combined with the functional characteristics of the memory control module. Using the verification strategy of software simulation and FPGA board level verification, the verification platform is built, and the corresponding verification scheme is put forward according to the concrete function of the storage control module, and the function simulation is carried out with Modelsim tool. The results show that the memory control module can complete the multiprocessor access to the off-chip memory SSRAM.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333;TN47
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，本文編號：2121167
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