本文選題：片上網(wǎng)絡(luò) + 路由器　； 參考：《武漢理工大學(xué)》2013年碩士論文

【摘要】：片上網(wǎng)絡(luò)(Network-on-Chip, NoC)作為一個新的設(shè)計方法被提出,它彌補(bǔ)了片上系統(tǒng)(System-on-Chip, SoC)帶來的一系列問題：可擴(kuò)展性差、總線通訊效率低、單一時鐘同步等。NoC采用全局異步--局部同步的通訊機(jī)制,不僅有良好的可擴(kuò)展性和可預(yù)測性,還提供了高帶寬的并行通訊能力。 隨著對NoC不斷深入的研究,給設(shè)計者們引入了新的機(jī)遇和挑戰(zhàn),例如功耗和穩(wěn)定性。為了獲得高性能的片上網(wǎng)絡(luò),大量的緩存被利用到片上網(wǎng)絡(luò)通信中,造成了緩存冗余和功耗泄露。并且,研究發(fā)現(xiàn)當(dāng)片上網(wǎng)絡(luò)中緩存達(dá)到一定數(shù)目時,片上網(wǎng)絡(luò)的性能并不是隨著緩存隊列數(shù)目的增加而線性增長的,反而對整個網(wǎng)絡(luò)造成負(fù)面影響。研究表明片上網(wǎng)絡(luò)中所有路由器的緩存隊列占據(jù)了整個網(wǎng)絡(luò)緩存的60%左右,緩存在時間和空間上利用率低,從而導(dǎo)致了大量的功耗泄漏,更重要的是路由器中的緩存隊列不能共享嚴(yán)重造成了功耗浪費(fèi)。因此,本文對通用路由器內(nèi)部結(jié)構(gòu)進(jìn)行優(yōu)化,設(shè)計出緩存共享的路由器。該路由器減少計算單元(Processing Element. PE)輸入物理通道的緩存隊列,使其與其他端口的輸入物理通道的緩存隊列共享,提高了緩存的利用率,降低功耗和硬件開銷。 基于緩存共享的路由器,本文提出了容錯的路由算法。由于片上網(wǎng)絡(luò)體系結(jié)構(gòu)對路由節(jié)點(diǎn)的錯誤很敏感,一旦有鏈路或者路由器出現(xiàn)問題,核之間的通信就不能得到保證。尤其隨著片上網(wǎng)絡(luò)IP核的增加,路由器和鏈路故障會對整個網(wǎng)絡(luò)造成不可想象的災(zāi)難。所以路由算法是否具有容錯能力影響整個體系結(jié)構(gòu)的穩(wěn)定性。本文提出了一個融合緩存共享路由器的容錯路由算法,該算法在PE輸入物理通道分別與X維、Y維輸入物理通道緩存共享的情況下,通過動態(tài)閾值來控制整個網(wǎng)絡(luò)的擁塞,在最短路徑中選擇沒有故障和擁塞度相對較小的路徑,將數(shù)據(jù)包從源節(jié)點(diǎn)發(fā)送到目的節(jié)點(diǎn),改善了整個網(wǎng)絡(luò)的延遲,提高了穩(wěn)定性,在一定程度上降低了功耗開銷。 最后,本文利用周期精確的Noxim模擬器,在三種不同的流量模式下,分別對本文的路由算法、XY路由算法和DyAD路由算法進(jìn)行了性能和功耗上的評估,仿真結(jié)果發(fā)現(xiàn)本文的路由算法性能都優(yōu)于其它兩種路由算法。在隨機(jī)流量模式下,針對故障節(jié)點(diǎn)數(shù)量的不同,實驗結(jié)果顯示容錯路由算法相比NF路由算法和DyAD路由算法有較高的穩(wěn)定性,功耗相比前兩者要節(jié)省10%左右功耗開銷。
[Abstract]:As a new design method, Network-on-Chip (NOC) is proposed to make up for a series of problems caused by System-on-Chip (SoC): poor scalability and low bus communication efficiency. Single clock synchronization. NOC adopts global asynchronous-local synchronous communication mechanism which not only has good scalability and predictability but also provides high bandwidth parallel communication capability. With the in-depth study of NOC, new opportunities and challenges, such as power consumption and stability, have been introduced to designers. In order to obtain high performance on-chip network, a large number of buffers are utilized in on-chip network communication, resulting in cache redundancy and power leakage. Furthermore, it is found that the performance of the on-chip network does not increase linearly with the increase of the number of cache queues, but has a negative impact on the whole network when the cache in the on-chip network reaches a certain number. The research shows that the cache queue of all routers in the on-chip network accounts for about 60% of the whole network cache, and the cache utilization is low in time and space, which leads to a lot of power leakage. More importantly, cache queues in routers can not be shared, resulting in a serious waste of power. Therefore, this paper optimizes the internal structure of general router and designs a cache-sharing router. The router reduces processing element. The PE) inputs the cache queue of the physical channel to share it with the cache queue of the input physical channel of other ports, which improves the utilization of the cache, reduces the power consumption and hardware overhead. Based on cache sharing router, this paper proposes a fault-tolerant routing algorithm. Because the on-chip network architecture is sensitive to the errors of routing nodes, the communication between cores cannot be guaranteed once there is a link or router problem. Especially with the increase of IP core, router and link failure will cause unimaginable disaster to the whole network. Therefore, whether the routing algorithm has fault-tolerant ability affects the stability of the whole architecture. In this paper, a fault-tolerant routing algorithm combining buffer sharing router is proposed. Under the condition that PE input physical channel and X dimensional Y dimensional input physical channel cache are shared separately, the congestion of the whole network is controlled by dynamic threshold. In the shortest path, the path with no fault and relatively small congestion degree is chosen, and the packet is sent from the source node to the destination node, which improves the delay of the whole network, improves the stability, and reduces the power consumption to a certain extent. Finally, using the periodic accurate Noxim simulator, the performance and power consumption of the routing algorithms (XY routing algorithm and DyAD routing algorithm) are evaluated in three different traffic modes. Simulation results show that the performance of the routing algorithm is better than the other two routing algorithms. In the random traffic mode, the experimental results show that the fault-tolerant routing algorithm is more stable than NF routing algorithm and DyAD routing algorithm, and the power consumption is about 10% less than that of the former two algorithms.
【學(xué)位授予單位】：武漢理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TN47;TP302.8

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本文編號：2114866