本文選題：SHA-3 + BLAKE��； 參考：《復(fù)旦大學(xué)》2012年碩士論文

【摘要】：隨著移動(dòng)互聯(lián)網(wǎng)的發(fā)展,數(shù)字簽名、密碼驗(yàn)證等算法在手機(jī)、平板電腦等嵌入式平臺(tái)上得到了越來越廣的應(yīng)用。雜湊算法作為這些算法的基礎(chǔ),其重要性也越來越高。但是近年來廣為使用的MD5和SHA-1雜湊算法受到了嚴(yán)重的挑戰(zhàn),美國NIST為應(yīng)對(duì)這種情況展開了SHA-3標(biāo)準(zhǔn)的競(jìng)賽,以期得到一種新的雜湊算法替代SHA-1和改進(jìn)不大的SHA-2。BLAKE算法為SHA-3競(jìng)賽最后一輪的候選算法,具有一系列的優(yōu)勢(shì),但是在嵌入式平臺(tái)上依然缺乏高效而靈活的實(shí)現(xiàn),阻礙了它的應(yīng)用。 所以,本文以面向在嵌入式系統(tǒng)上高效地實(shí)現(xiàn)BLAKE算法為研究目標(biāo),致力于設(shè)計(jì)一款為加速BLAKE算法的特殊指令集處理器(Application Specific Instruction-set Processor或ASIP)。針對(duì)這一目標(biāo),本文首先根據(jù)BLAKE算法的描述建立了模型,然后在前人的基礎(chǔ)上整理和改進(jìn),得出了一整套方法結(jié)合自動(dòng)化的算法和人工干預(yù)的手段,在一定約束條件下在G函數(shù)的范圍內(nèi)進(jìn)行指令空間探索,從而獲得專門用于G函數(shù)的優(yōu)化指令集、相應(yīng)的支持特殊硬件及匹配的輸入輸出方式,用于指導(dǎo)專用指令集處理器硬件的設(shè)計(jì)。然后,根據(jù)理論分析的結(jié)果,本文設(shè)計(jì)了一款面向嵌入式應(yīng)用的ASIP,并從硬件和軟件2個(gè)方面詳細(xì)描述了該處理器的設(shè)計(jì),實(shí)現(xiàn)了在嵌入式系統(tǒng)上高效地實(shí)現(xiàn)BLAKE算法的研究目標(biāo)。 為驗(yàn)證本文所設(shè)計(jì)的解決方案,帶有異步功能單元特殊硬件的處理器實(shí)現(xiàn)則經(jīng)過Design Compiler邏輯綜合并通過TSMC65nm工藝流片來實(shí)現(xiàn)和驗(yàn)證。經(jīng)邏輯綜合結(jié)果表明,本文設(shè)計(jì)的專用處理器理論上最高可以運(yùn)行于1001M Hz的頻率之上,在此頻率下32位和64位BLAKE算法程序的吞吐率分別可以達(dá)到335Mbps和176Mbps,周期數(shù)每字節(jié)則分別可以達(dá)到23.81和45.39。專用處理器所占面積在案例A和案例B下分別為28.48和28.07千等效門。流片結(jié)果經(jīng)測(cè)試,在1.3V核心電壓下,芯片可以134mW功率工作在890Mhz頻率下,吞吐率指標(biāo)達(dá)到300Mbps。本文設(shè)計(jì)達(dá)到了預(yù)期目標(biāo),在高效低開銷實(shí)現(xiàn)BLAKE算法的同時(shí),同時(shí)具有很高的擴(kuò)展性可兼顧SHA-3族的其他候選算法,非常適用于嵌入式系統(tǒng)的安全應(yīng)用,具有較高的應(yīng)用前景。
[Abstract]:With the development of mobile Internet, digital signature, cryptographic verification and other algorithms have been more and more widely used in mobile phones, tablets and other embedded platforms. As the basis of these algorithms, hash algorithms are becoming more and more important. However, MD5 and SHA-1 hashing algorithms, which have been widely used in recent years, have been seriously challenged. NIST in the United States has launched a competition for SHA-3 standards to deal with this situation. In order to obtain a new hash algorithm to replace SHA-1 and the improved SHA-2.BLAKE algorithm as a candidate algorithm for the last round of SHA-3 competition, it has a series of advantages, but it still lacks efficient and flexible implementation on embedded platform, which hinders its application. Therefore, aiming at the efficient implementation of BLAKE algorithm on embedded system, this paper aims to design a special instruction set processor (Application specific Instruction-set processor or ASIP) for accelerating BLAKE algorithm. According to the description of BLAKE algorithm, this paper first establishes the model, and then, on the basis of the former, a complete set of methods combined with automated algorithm and manual intervention is obtained. Under certain constraints, the instruction space is explored within the scope of G function, and the optimized instruction set for G function is obtained, and the corresponding input and output modes supporting special hardware and matching are obtained. It is used to guide the design of special instruction set processor hardware. Then, according to the results of theoretical analysis, an embedded application oriented ASIP is designed in this paper, and the design of the processor is described in detail from two aspects of hardware and software. The research goal of BLAKE algorithm is realized efficiently on embedded system. In order to verify the solution designed in this paper, the implementation of the processor with special hardware of asynchronous function unit is implemented and verified by Design Compiler logic synthesis and TSMC 65nm process flow chip. The results of logic synthesis show that the special purpose processor designed in this paper can run up to 1001mHz in theory. At this frequency, the throughput of 32-bit and 64-bit BLAKE programs can reach 335Mbps and 176Mbpss respectively, and the number of cycles per byte can reach 23.81 and 45.39respectively. The area occupied by dedicated processors is 28.48 and 28.07 thousand equivalent gates under case A and case B, respectively. The test results show that the chip can work at 890MHz frequency at 134MW power at 1.3V core voltage, and the throughput can reach 300Mbps. The design of this paper has achieved the expected goal. The BLAKE algorithm is implemented with high efficiency and low overhead. At the same time, it has high expansibility and can take account of other candidate algorithms of SHA-3 family. It is very suitable for the security application of embedded system and has a high application prospect.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332
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本文編號(hào)：2108849