本文選題：SRAM + 漏電流�。� 參考：《安徽大學(xué)》2017年碩士論文

【摘要】：隨著半導(dǎo)體工藝的進(jìn)步,SRAM朝著高速,低功耗的方向不斷邁進(jìn)。然而,存在于位線上的漏電流也越來越大。漏電流的增大導(dǎo)致了 SRAM性能的下降。尤其是,當(dāng)泄漏電流的大小達(dá)到一個(gè)臨界值時(shí),會(huì)造成讀失效。因此,對(duì)漏電流的研究至關(guān)重要。本文的主要工作如下:1、本文首先介紹了 SRAM的三種基本操作,分別是讀操作,寫操作和保持操作。然后介紹了國(guó)內(nèi)外幾種經(jīng)典的漏流應(yīng)對(duì)技術(shù),包括BLC技術(shù)、X-calibration技術(shù)以及位線正反饋補(bǔ)償技術(shù)。詳細(xì)分析了它們的工作原理,并且總結(jié)了各自的優(yōu)缺點(diǎn)。2、為了加快靈敏放大器(SA)的讀取速度,本文提出了一種基于X-calibration(XC)電路的改進(jìn)方案,即加法校準(zhǔn)電路(Additive Calibration,AC)。通過實(shí)驗(yàn)手段,證實(shí)了加法校準(zhǔn)電路能夠花費(fèi)更少的時(shí)間來讀出數(shù)據(jù),提升了 SRAM的性能。不過這種改動(dòng)能承受的漏電流的大小和XC相近。而且需要一個(gè)較長(zhǎng)的漏流檢測(cè)階段,不適合工作在高頻下。不過AC方案依然有著改進(jìn)的空間,來克服上述缺點(diǎn)。3、本文進(jìn)一步對(duì)2中的電路加以改進(jìn),從時(shí)序入手,增加了二次預(yù)充的環(huán)節(jié),得到NAC電路。二次改進(jìn)后的NAC方案,它最主要的特點(diǎn)在于時(shí)序的調(diào)整,比XC技術(shù)多了一個(gè)操作。仿真結(jié)果說明,NAC的優(yōu)點(diǎn)不僅在于同加法校準(zhǔn)電路一樣提高了 SA的驅(qū)動(dòng)能力。更重要的,在于它能比XC承受更大的漏流,這符合當(dāng)今漏流補(bǔ)償技術(shù)的發(fā)展趨勢(shì)。在SMIC65nm工藝下,基于本文提出的技術(shù),具體實(shí)現(xiàn)電路的最終仿真結(jié)果是.·可承受漏流的能力相比傳統(tǒng)SRAM結(jié)構(gòu)和X-calibration技術(shù)分別提升了 119%和45.5%。
[Abstract]:With the progress of semiconductor technology, SRAM is moving towards high speed and low power consumption. However, the leakage current on the bit line is also increasing. The increase of leakage current leads to the degradation of SRAM performance. In particular, read failure occurs when the leakage current reaches a critical value. Therefore, the study of leakage current is very important. The main work of this paper is as follows: 1. This paper first introduces three basic operations of SRAM, which are read operation, write operation and hold operation. Then several classical leakage response technologies are introduced, including BLC X-Calibration technology and bit line positive feedback compensation technology. In order to speed up the reading speed of the sensitive amplifier (SA), an improved scheme based on X-Calibration (XC) is proposed, which is called Additive Calibration AC. The experimental results show that the additive calibration circuit can take less time to read out the data and improve the performance of SRAM. However, this change can withstand the size of the leakage current and XC similar. And it needs a long leakage detection stage, which is not suitable to work at high frequency. However, there is still room for improvement in AC scheme to overcome the above shortcomings. In this paper, the circuit in 2 is further improved. Starting from the timing, the secondary precharge link is added to obtain the NAC circuit. The second improved NAC scheme, whose main feature is timing adjustment, has one more operation than XC technology. The simulation results show that the advantage of NAC is not only that it improves the driving ability of SA as well as the additive calibration circuit. More importantly, it can withstand larger leakage than XC, which is in line with the current trend of leakage compensation technology. In SMIC65nm process, based on the technology proposed in this paper, the final simulation results of the circuit are as follows: compared with the traditional SRAM structure and X-Calibration technology, the capability of withstanding leakage current is improved by 119% and 45.55.5respectively.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP333

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相關(guān)期刊論文 前1條

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本文編號(hào)：2101094