本文選題：嵌入式 + 堆棧處理器��； 參考：《南京航空航天大學(xué)》2012年碩士論文

【摘要】：嵌入式微處理器作為嵌入式系統(tǒng)的核心，其重要性不言而喻。堆棧處理器是一種專門面向嵌入式控制領(lǐng)域的處理器，其所有執(zhí)行過程均依賴于硬件支持的堆棧，而不是通用寄存器。因此，相比較于傳統(tǒng)的RISC和CISC處理器，堆棧處理器具有以下三點(diǎn)優(yōu)勢(shì)：（1）避免了上下文切換帶來的開銷，這是因?yàn)樘幚砥鞯倪\(yùn)行不依賴于大量的通用寄存器；（2）尋址方式非常簡(jiǎn)單，這是因?yàn)閹缀跛兄噶疃际?操作數(shù)指令；（3）更加適合執(zhí)行具有深度遞歸或者嵌套特征的程序，這是因?yàn)榫哂袑ｉT的硬件堆棧支持子程序調(diào)用與返回。目前國(guó)內(nèi)鮮有相關(guān)研究報(bào)道，因此研究并實(shí)現(xiàn)出高性能的堆棧處理器具有重要的意義。 本文圍繞堆棧處理器做了兩方面的工作：一是設(shè)計(jì)與實(shí)現(xiàn)，二是應(yīng)用。在堆棧處理器的設(shè)計(jì)與實(shí)現(xiàn)方面，，本文首先采用基于FPGA的方式設(shè)計(jì)與實(shí)現(xiàn)了一款16位單周期堆棧處理器。該處理器包含兩個(gè)堆棧：執(zhí)行數(shù)學(xué)表達(dá)式的數(shù)據(jù)堆棧和支持子程序調(diào)用的返回堆棧。它具有結(jié)構(gòu)緊湊、系統(tǒng)復(fù)雜度低、主頻性能高以及代碼體積小等優(yōu)點(diǎn)。其次，為了提高處理器性能，本文將流水線技術(shù)應(yīng)用于單周期堆棧處理器，設(shè)計(jì)與實(shí)現(xiàn)了三級(jí)流水線的堆棧處理器，詳細(xì)討論了流水線技術(shù)帶來的冒險(xiǎn)問題，并給出了解決方法。在堆棧處理器的應(yīng)用方面，本文以單周期堆棧處理器與流水線堆棧處理器為核心分別構(gòu)建出了SOPC，為SOPC設(shè)計(jì)了總線控制器，中斷控制器以及多種外設(shè)。論文詳細(xì)介紹了SOPC的架構(gòu)，描述了每一種外設(shè)的功能。堆棧處理器僅使用常規(guī)的訪存指令就可以控制中斷控制器與所有外設(shè)。 本文的所有設(shè)計(jì)均采用Verilog硬件描述語(yǔ)言進(jìn)行RTL級(jí)描述，采用ModelSim軟件進(jìn)行功能仿真，采用Synplify軟件進(jìn)行綜合。仿真與綜合的結(jié)果證明本文設(shè)計(jì)的堆棧處理器與SOPC功能正確。在以XC5VLX110T為目標(biāo)芯片時(shí)，單周期堆棧處理器與流水線堆棧處理器的主頻分別達(dá)到了146.7MHz與257.1MHz。結(jié)果優(yōu)于國(guó)外同類設(shè)計(jì)，性能令人滿意。
[Abstract]:As the core of embedded system, the importance of embedded microprocessor is self-evident. Stack processor is a special processor for embedded control domain. All of its execution process depends on the stack supported by hardware instead of general register. Therefore, compared with the traditional RISC and CISC processors, the stack processor has the following three advantages: (1) the overhead caused by context switching is avoided because the processor does not rely on a large number of general registers; (2) the addressing method is very simple, because almost all instructions are zero Operand instructions; (3) it is more suitable to execute programs with deep recursion or nesting characteristics because of the special hardware stack support subroutine call and return. There are few reports in China, so it is very important to study and implement high performance stack processor. This paper has done two aspects of work around stack processor: one is design and implementation, the other is application. In the aspect of stack processor design and implementation, this paper first designs and implements a 16-bit single cycle stack processor based on FPGA. The processor consists of two stacks: a data stack that executes mathematical expressions and a return stack that supports subroutine calls. It has the advantages of compact structure, low system complexity, high main frequency performance and small code size. Secondly, in order to improve the processor performance, this paper applies pipeline technology to single-cycle stack processor, designs and implements three-stage pipeline stack processor, discusses the adventure problem brought by pipeline technology in detail. The solution is given. In the application of stack processor, this paper constructs SOPC based on single cycle stack processor and pipeline stack processor, and designs bus controller, interrupt controller and many peripheral devices for SOPC. The architecture of SOPC is introduced in detail, and the functions of each peripheral are described. The stack processor can control the interrupt controller and all peripherals using only regular memory access instructions. All the designs in this paper are described at RTL level by Verilog hardware description language, functional simulation by ModelSim software and synthesis by Synplify software. The results of simulation and synthesis show that the stack processor and SOPC designed in this paper are correct. With XC5VLX110T as the target chip, the main frequency of single-cycle stack processor and pipeline stack processor are 146.7 MHz and 257.1 MHz respectively. The result is superior to the similar design abroad and the performance is satisfactory.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TN47;TP368.1

【參考文獻(xiàn)】

相關(guān)期刊論文 前3條

1 何賓;王瑜;;基于Xilinx MicroBlaze多核嵌入式系統(tǒng)的設(shè)計(jì)[J];電子設(shè)計(jì)工程;2011年13期

2 于海;樊曉椏;張盛兵;;32位RISC微處理器FPGA驗(yàn)證平臺(tái)設(shè)計(jì)與實(shí)現(xiàn)[J];計(jì)算機(jī)工程與應(yīng)用;2007年05期

3 汪永威;樊曉椏;黃小平;;32位RISC微處理器中分支預(yù)測(cè)器的硬件實(shí)現(xiàn)[J];計(jì)算機(jī)應(yīng)用研究;2009年02期

相關(guān)博士學(xué)位論文 前3條

1 古海云;可重構(gòu)SoC設(shè)計(jì)技術(shù)研究[D];東南大學(xué);2006年

2 李琳;音頻感知編碼模型及關(guān)鍵技術(shù)的研究[D];中國(guó)科學(xué)技術(shù)大學(xué);2008年

3 陳利光;適合于硬件進(jìn)化的FPGA平臺(tái)設(shè)計(jì)實(shí)現(xiàn)[D];復(fù)旦大學(xué);2009年

本文編號(hào)：2087875