本文選題：余數(shù)系統(tǒng) + 模2~n-2~k±1加法器��； 參考：《電子科技大學(xué)》2013年碩士論文

【摘要】：過(guò)去的十幾年，超大規(guī)模集成電路的集成度的提高主要是依賴于工藝特征尺寸的減小，但如今的半導(dǎo)體工藝已經(jīng)到了極限的水平，而且又隨著用戶對(duì)電子產(chǎn)業(yè)的要求越來(lái)越高，因此集成電路亟需解決其處理速度、面積和功耗之間如何權(quán)衡的問(wèn)題。 余數(shù)系統(tǒng)具有并行處理的性質(zhì)，它可以將原本單一的、復(fù)雜的處理單元?jiǎng)澐殖啥鄠�(gè)獨(dú)立的、簡(jiǎn)單的處理通道，將這種方式應(yīng)用在集成電路設(shè)計(jì)中，可以在不增大面積開(kāi)銷的基礎(chǔ)上來(lái)提高集成電路的運(yùn)行速度。對(duì)于余數(shù)系統(tǒng)，它的基本運(yùn)算單元是模加和模乘，因此模加和模乘的算法是影響基于余數(shù)系統(tǒng)的集成電路性能最主要的因素。 本文主要針對(duì)余數(shù)系統(tǒng)中的模加法器和模乘法器的設(shè)計(jì)展開(kāi)了深入的研究，并且這些設(shè)計(jì)都能在一個(gè)時(shí)鐘周期內(nèi)完成，對(duì)今后余數(shù)系統(tǒng)能更好地應(yīng)用在集成電路中奠定了基礎(chǔ)。 為了滿足現(xiàn)代信號(hào)處理的復(fù)雜度，形式為2~n-2~k±1的余數(shù)基已經(jīng)成為了余數(shù)系統(tǒng)中主要的通道，這也就意味著對(duì)這種形式的余數(shù)基的模加法器和模乘法器的研究是非常重要的。余數(shù)系統(tǒng)中最常用的通道包括{2~n+1,2~n,2~n-1}、{2~(2n)+1,2~n,2~(2n)-1}、{2~(n+1)+1,2~n,2~(n+1)-1}等，，而且對(duì)于類似上述這些常用的余數(shù)基通道，它們的動(dòng)態(tài)范圍都是2~n-2~k形式。因此對(duì)于這些余數(shù)系統(tǒng)，在其向二進(jìn)制運(yùn)算系統(tǒng)的轉(zhuǎn)換過(guò)程中，模為2~n-2~k形式的運(yùn)算單元的集成電路實(shí)現(xiàn)性能是決定這些余數(shù)系統(tǒng)的后向轉(zhuǎn)換電路性能的主要因素之一，又由于后向轉(zhuǎn)換對(duì)整個(gè)余數(shù)系統(tǒng)的集成電路性能的影響也非常大，因此一個(gè)優(yōu)良性能的模2~n-2~k乘法器對(duì)整個(gè)余數(shù)系統(tǒng)也有非常大的意義。 因此本文針對(duì)模2~n-2~k±1和2~n-2~k運(yùn)算單元分別提出了其相應(yīng)的算法，具體如下： (1)本文第三章主要是針對(duì)形式為2~n-2~k±1的模加法器進(jìn)行了優(yōu)化設(shè)計(jì)，這類模加法器是基于進(jìn)位修正和并行前綴運(yùn)算結(jié)構(gòu)基礎(chǔ)上提出的，它們都可以劃分為四個(gè)基本的單元，分別為數(shù)據(jù)預(yù)處理、進(jìn)位生成、進(jìn)位修正和求和單元。其中模2~n-2~k±1加法器是根據(jù)A+B+T的最高進(jìn)位對(duì)A+B+T的進(jìn)位信息進(jìn)行修正的，而模2~n-2~k+1加法器是根據(jù)A+B+T+2~n的最高進(jìn)位對(duì)A+B+T+2~n的進(jìn)位信息進(jìn)行修正的。因此模2~n-2~k+1加法器與模2~n-2~k±1加法器相比，它的數(shù)據(jù)預(yù)處理單元要多一級(jí)CSA(Carry-Save Adder)壓縮陣列的處理。 (2)本文在第四章提出了模2~n-2~k乘法器的算法，該乘法器巧妙地結(jié)合了兩類修正方法，最終消除了求模操作。 (3)本文在第四章還提出了模2~n-2~k+1乘法器的算法，該乘法器直接對(duì)兩乘數(shù)的二進(jìn)制乘積結(jié)果進(jìn)行多次修正，最終將其轉(zhuǎn)化為一個(gè)n位的模加法運(yùn)算。 最后本文對(duì)所有提出的算法和與之進(jìn)行對(duì)比的文獻(xiàn)中的設(shè)計(jì)分別采用Verilog硬件描述語(yǔ)言進(jìn)行建模，并在TSMC90納米工藝下采用Design Compiler(DC)工具對(duì)這些Verilog模型進(jìn)行邏輯綜合，最后對(duì)其面積和時(shí)延報(bào)告進(jìn)行分析與比較，這些比較結(jié)果可以充分說(shuō)明本文提出的所有算法都具有較好的“面積x時(shí)延”特性，更適合用于集成電路的實(shí)現(xiàn)。
[Abstract]:In the past decade, the integration of VLSI is mainly dependent on the reduction of process feature size, but now the semiconductor technology has reached the limit level, and with the increasing demand for the electronic industry, the integrated circuit needs to solve the right between the processing speed, the area and the power consumption. The question of balance.
The remainder system has the nature of parallel processing. It can divide the original single, complex processing unit into multiple independent, simple processing channels. This method is applied to the design of integrated circuits. It can improve the running speed of the integrated circuit without increasing the area overhead. For the remainder system, its basic operation Modules are modular addition and modular multiplication, so the algorithm of modular addition and modular multiplication is the most important factor affecting the performance of integrated circuits based on residue systems.
This paper mainly focuses on the design of modulo adder and modular multiplier in the remainder system, and these designs can be completed in one clock cycle, which lays a foundation for the better application of the remainder system in the integrated circuit.
In order to meet the complexity of modern signal processing, the 2~n-2~k + 1 remainder base has become the main channel in the remainder system, which means that the research of modulo and modular multipliers for this form is very important. The most commonly used channels in the remainder system include {2~n+1,2~n, 2~n-1}, {2~ (2n) +1,2~n, 2~ (2n). ) -1}, {2~ (n+1) +1,2~n, 2~ (n+1) -1} and so on, and their dynamic range is 2~n-2~k form for these commonly used remainder based channels. Therefore, for these remainder systems, the performance of the integrated circuits that modulo the operation unit in the form of 2~n-2~k in its conversion to the binary operation system determines the remainder system One of the main factors of the performance of the back conversion circuit is also due to the great influence of backward conversion on the performance of the integrated circuit of the whole remainder system, so a good performance model 2~n-2~k multiplier also has great significance for the whole remainder system.
Therefore, the corresponding algorithm is proposed for module 2~n-2~k + 1 and 2~n-2~k operation unit respectively.
(1) the third chapter of this paper is mainly designed for the mode adder with the form of 2~n-2~k + 1. The modular adder is based on the input correction and the parallel prefix operation structure. All of them can be divided into four basic units, which are data preprocessing, the carry generation, the advance correction and the summation unit. Among them, the modulus 2~n- The 2~k + 1 adder modifies the input information of the A+B+T based on the maximum entry of the A+B+T, and the modular 2~n-2~k+1 adder modifies the input information of the A+B+T+2~n based on the maximum entry of the A+B+T+2~n. Therefore, the modular 2~n-2~k+1 adder is more CSA (Carry-Save Add) than the modulus 2~n-2~k + 1 adder. Er) the processing of the compressed array.
(2) in the fourth chapter, we propose the algorithm of modular 2~n-2~k multiplier, which cleverly combines two kinds of correction methods, and ultimately eliminates the module operation.
(3) in the fourth chapter, the algorithm of the modular 2~n-2~k+1 multiplier is also proposed. The multiplier directly corrections the result of the binary product of the two multiplier and eventually transforms it into a n bit model addition.
Finally, this paper uses Verilog hardware description language to model all the proposed algorithms and the comparison in the literature, and uses the Design Compiler (DC) tool to integrate these Verilog models under the TSMC90 nanotechnology. Finally, the area and time delay report are analyzed and compared. These comparisons are made. The results show that all the algorithms proposed in this paper have better "area X delay" characteristics and are more suitable for the realization of integrated circuits.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332.2

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 ;An efficient RNS parity checker for moduli set{2~n-1,2~n+1,2~(2n)+1}and its applications[J];Science in China(Series F:Information Sciences);2008年10期

本文編號(hào)：2069658