本文選題：片間直連 + Cache一致性�。� 參考：《計(jì)算機(jī)工程》2017年10期

【摘要】：目前廣泛采用的廣播協(xié)議帶寬需求較高,目錄協(xié)議訪存延遲較大,不適用于國產(chǎn)服務(wù)器處理器片間直連接口帶寬相對較低、延遲較高的應(yīng)用場景。為此,基于片內(nèi)目錄、片間Token廣播的雙層異構(gòu)混合一致性協(xié)議,應(yīng)用訪存局部性原理,對片間請求廣播范圍進(jìn)行預(yù)測研究,提出一種HP-SRW協(xié)議。實(shí)驗(yàn)結(jié)果表明,與兩級目錄協(xié)議相比,該協(xié)議時(shí)間性能提高8.9%,帶寬需求降低3.1%,與混合協(xié)議相比時(shí)間性能略有提升,帶寬需求降低30.6%,與Token協(xié)議相比,HP-SRW協(xié)議以4.7%的時(shí)間性能為代價(jià),帶寬需求降低66.5%。
[Abstract]:At present, the widely used broadcast protocol has a high bandwidth requirement, and the directory protocol has a large memory access delay. It is not suitable for applications where the bandwidth of the direct-to-chip connection port between domestic server processors is relatively low and the delay is high. In this paper, based on intra-chip directory and inter-chip token broadcast protocol, a novel HP-SRW protocol is proposed, which is based on the principle of memory access and locality, and predicts the range of inter-chip request broadcasting. The experimental results show that compared with the two-level directory protocol, the time performance of the protocol is improved by 8.9, the bandwidth requirement is reduced by 3.1 percent, the time performance is slightly improved compared with the hybrid protocol, and the bandwidth requirement is reduced by 30.6. compared with the token protocol, the HP-SRW protocol costs 4.7% time performance. Bandwidth requirements were reduced by 66.5.
【作者單位】： 上海高性能集成電路設(shè)計(jì)中心;
【基金】：“核高基”重大專項(xiàng)“超級計(jì)算機(jī)處理器研發(fā)”(2013ZX0102-8001-001-001)
【分類號】：TN915.04;TP332
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本文編號：2057065