發(fā)布時(shí)間：2018-06-23 02:53

  本文選題：同構(gòu)通用流體系結(jié)構(gòu) + 流核心�。� 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：多核體系結(jié)構(gòu)正在飛速發(fā)展，從少量的復(fù)雜多核架構(gòu)到面向計(jì)算密集型應(yīng)用的簡(jiǎn)單眾核架構(gòu)，近年來(lái)，，業(yè)界又出現(xiàn)了CPU+GPU的異構(gòu)架構(gòu)，試圖同時(shí)發(fā)揮兩者的優(yōu)勢(shì)，但是該架構(gòu)功耗較大，CPU和GPU的分離存儲(chǔ)導(dǎo)致性能瓶頸。片內(nèi)融合技術(shù)的出現(xiàn)解決了存儲(chǔ)分離導(dǎo)致的數(shù)據(jù)通信延時(shí)問題，然而異構(gòu)的融合架構(gòu)使得資源無(wú)法充分利用�；谝陨媳尘埃髡咚鶎僬n題組提出了同構(gòu)通用流處理器體系結(jié)構(gòu)：片內(nèi)集成多個(gè)同構(gòu)流多核，流多核可根據(jù)具體應(yīng)用配置為CPU或流處理器的一部分。片內(nèi)共享存儲(chǔ)消除了CPU與流處理器分離存儲(chǔ)帶來(lái)的數(shù)據(jù)傳輸開銷，采用64位RISC核增強(qiáng)可編程性，動(dòng)態(tài)配置流多核的功能增大了芯片資源利用率。 在現(xiàn)代處理器的設(shè)計(jì)研究過程中，模擬器發(fā)揮著舉足輕重的作用。在設(shè)計(jì)初期，可以根據(jù)模擬器判斷體系結(jié)構(gòu)設(shè)計(jì)是否滿足功能要求；在完成RTL級(jí)模型編碼以后，可以進(jìn)行軟硬件協(xié)同驗(yàn)證；在處理器投片前，模擬器可以為上層軟件提供仿真環(huán)境，提前系統(tǒng)軟件、編譯器和應(yīng)用軟件的開發(fā)；同時(shí)，模擬器可以統(tǒng)計(jì)應(yīng)用程序執(zhí)行過程中的各項(xiàng)詳細(xì)信息，有助于應(yīng)用程序的優(yōu)化和體系結(jié)構(gòu)的研究。 出于課題組對(duì)同構(gòu)通用流處理器體系結(jié)構(gòu)的研究需要，以及模擬器對(duì)體系結(jié)構(gòu)研究和編譯器等軟件開發(fā)的重要性，本文面向同構(gòu)通用流處理器體系結(jié)構(gòu)的基本單元MB64流核心，進(jìn)行體系結(jié)構(gòu)模擬器的設(shè)計(jì)與實(shí)現(xiàn)。 本文的主要工作包括以下三點(diǎn)： 1、設(shè)計(jì)實(shí)現(xiàn)MB64功能模擬器，能夠在cross-endian情況下正確加載ELF文件，能正確執(zhí)行帶分支延遲槽的分支指令，進(jìn)行簡(jiǎn)單的數(shù)據(jù)統(tǒng)計(jì)，為對(duì)應(yīng)結(jié)構(gòu)的編譯器設(shè)計(jì)提供實(shí)驗(yàn)環(huán)境。 2、設(shè)計(jì)實(shí)現(xiàn)了MB64性能模擬器，采用基于前瞻的動(dòng)態(tài)調(diào)度流水線，支持2位分支預(yù)測(cè)算法和BTB，使用tomasulo動(dòng)態(tài)調(diào)度算法，精確模擬帶分支延遲槽的分支指令，在錯(cuò)誤路徑恢復(fù)時(shí)，能保證延遲槽指令和分支指令以及imm特殊指令與立即數(shù)類指令的原子操作關(guān)系，進(jìn)行詳細(xì)的執(zhí)行信息和時(shí)序信息的數(shù)據(jù)統(tǒng)計(jì)，為體系結(jié)構(gòu)方面研究打下基礎(chǔ)。 3、對(duì)MB64體系結(jié)構(gòu)進(jìn)行特性分析，針對(duì)Cache容量、相聯(lián)度、BTB大小等體系結(jié)構(gòu)參數(shù)進(jìn)行實(shí)驗(yàn)，記錄參數(shù)變化對(duì)性能的影響，考慮硬件開銷進(jìn)行折中權(quán)衡，以實(shí)現(xiàn)最佳參數(shù)的選擇。最后利用快速推進(jìn)和動(dòng)態(tài)譯碼緩存技術(shù)，提高了MB64Sim的模擬速度。
[Abstract]:Multi-core architecture is developing rapidly, from a small number of complex multi-core architectures to simple multi-core architectures for computation-intensive applications. In recent years, the heterogeneous architecture of CPU GPU has emerged in the industry, trying to take advantage of both. However, the separation of CPU and GPU leads to performance bottleneck. The emergence of in-chip fusion technology solves the problem of data communication delay caused by storage separation. However, heterogeneous fusion architecture can not make full use of resources. Based on the above background, the author's research group proposes a general architecture of isomorphic stream processor, which integrates multiple isomorphic streams and cores, which can be configured as part of CPU or stream processor according to the specific application. In-chip shared storage eliminates the data transfer overhead caused by the separation of CPU and stream processor, and uses 64-bit RISC core to enhance the programmability. The dynamic configuration of stream multi-core function increases the utilization of chip resources. Simulator plays an important role in the design and research of modern processor. At the beginning of the design, we can judge whether the architecture design meets the functional requirements according to the simulator; after completing the RTL model coding, we can carry out the hardware and software co-verification; before the processor chip, The simulator can provide the simulation environment for the upper software, advance the development of the system software, compiler and application software, at the same time, the simulator can count the detailed information during the execution of the application. It is helpful for application optimization and architecture research. In order to meet the need of our research on the architecture of isomorphic universal stream processor and the importance of simulator to the research of architecture and the development of software such as compiler, this paper aims at the basic unit MB64 stream core of the architecture of isomorphic universal stream processor. Design and implement the architecture simulator. The main work of this paper includes the following three points: 1. The MB64 functional simulator is designed and implemented, which can load the cross-endian file correctly, execute the branch instruction with branch delay slot correctly, and carry out simple data statistics. 2. The MB64 performance simulator is designed and implemented, which adopts dynamic scheduling pipeline based on prospect, supports 2-bit branch prediction algorithm and BTBs, and uses tomasulo dynamic scheduling algorithm. The accurate simulation of branch instruction with branch delay slot can guarantee the atomic operation relationship between the delay slot instruction and branch instruction and the imm special instruction and the immediate class instruction when the error path is restored. The detailed data statistics of execution information and timing information are carried out to lay the foundation for the research of architecture. 3. The characteristic analysis of MB64 architecture is carried out. The effect of parameter changes on performance is recorded, and the trade-off between hardware overhead is considered in order to select the best parameters. At last, the simulation speed of MB64Sim is improved by using fast advance and dynamic decoding buffer technology.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

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本文編號(hào)：2055428