發(fā)布時(shí)間：2018-06-21 19:05

  本文選題：DSP64X + HPI　； 參考：《國防科學(xué)技術(shù)大學(xué)》2012年碩士論文

【摘要】：DSP64X是我校自主研制的一款高性能定點(diǎn)數(shù)字信號(hào)處理器。它在語音、圖形圖像、信號(hào)處理、通信等眾多領(lǐng)域有著廣闊的應(yīng)用前景�？膳渲弥鳈C(jī)并行接口（Host-PortInterface，簡(jiǎn)稱HPI）是DSP與外部系統(tǒng)進(jìn)行通信的一個(gè)重要并行接口部件。通過HPI，可以完成外部主設(shè)備系統(tǒng)與DSP內(nèi)部存儲(chǔ)空間的數(shù)據(jù)交換、DSP芯片的自舉以及調(diào)試。在主從雙機(jī)DSP應(yīng)用系統(tǒng)中，通過配置HPI接口，還可以直接進(jìn)行雙機(jī)通信。 本論文的主要研究?jī)?nèi)容和主要研究成果： ◆在研究各種可配置并行接口部件技術(shù)的基礎(chǔ)上，根據(jù)DSP64X的總體結(jié)構(gòu)和性能需求，完成了該款DSP中可配置主機(jī)并行接口部件的總體結(jié)構(gòu)設(shè)計(jì)和協(xié)議設(shè)計(jì)。 ◆基于DSP64X，設(shè)計(jì)實(shí)現(xiàn)了一款可配置的主機(jī)并行接口，實(shí)現(xiàn)了與DSP64X的EDMA、外設(shè)總線控制器、中斷控制器以及系統(tǒng)控制器的接口協(xié)議。HPI部件包含5個(gè)功能模塊，分別為：外部主機(jī)接口模塊、外設(shè)總線接口模塊、讀緩存控制模塊、寫緩存控制模塊和EDMA接口模塊。 ◆深入研究了部件內(nèi)部讀、寫緩存的結(jié)構(gòu)設(shè)計(jì)，，實(shí)現(xiàn)了乒乓結(jié)構(gòu)的多緩存異步對(duì)接技術(shù)，從而實(shí)現(xiàn)外部主機(jī)與DSP之間進(jìn)行并行、高速數(shù)據(jù)交換。 ◆基于當(dāng)前微處理器的主要驗(yàn)證策略和方法，以及HPI功能結(jié)構(gòu)特點(diǎn)的要求，完成本設(shè)計(jì)的模塊級(jí)、部件級(jí)和系統(tǒng)級(jí)的模擬驗(yàn)證，為主機(jī)接口開發(fā)了完備的測(cè)試功能代碼，并完成了不同層次的功能驗(yàn)證和時(shí)序驗(yàn)證，保證了可配置主機(jī)并行接口在功能上滿足設(shè)計(jì)需求和時(shí)序約束要求。 ◆協(xié)助完成了基于C7YC68013芯片的仿真測(cè)試平臺(tái)的設(shè)計(jì)，并在該平臺(tái)上完成了對(duì)于DSP64X芯片HPI部件的所有功能驗(yàn)證和測(cè)試。經(jīng)實(shí)際投片芯片測(cè)試，所設(shè)計(jì)的HPI部件功能正確，外部工作頻率可達(dá)200MHz，可支持16位、32位數(shù)據(jù)的并行傳輸，最高數(shù)據(jù)帶寬可達(dá)800MB。完全達(dá)到了芯片總體設(shè)計(jì)的要求。
[Abstract]:DSP 64X is a high-performance fixed-point digital signal processor developed by our university. It has a broad application prospect in many fields, such as voice, graphics and image, signal processing, communication and so on. Configurable Host parallel Interface (HPI) is an important parallel interface component for DSP to communicate with external systems. Through HPI, the self-booting and debugging of DSP chip of data exchange between the external main equipment system and the internal storage space of DSP can be completed. In the Master-Slave dual DSP application system, by configuring the HPI interface, the communication between two computers can be carried out directly. The main research contents and results of this thesis are as follows: based on the research of various configurable parallel interface components, according to the overall structure and performance requirements of DSP64X, The overall structure design and protocol design of the configurable host parallel interface in the DSP are completed. Based on DSP64X, a configurable host parallel interface is designed and implemented, and the EDMA-peripheral bus controller with DSP64X is realized. The interface protocol of interrupt controller and system controller .HPI consists of five functional modules: external host interface module, peripheral bus interface module, read buffer control module. Write buffer control module and EDMA interface module. In this paper, the structure design of internal read and write cache is deeply studied, and the asynchronous docking technology of ping-pong multi-cache is realized, so that the parallel between external host and DSP is realized. High speed data exchange. Based on the main verification strategies and methods of current microprocessor and the requirements of HPI function structure, the simulation verification of module level, component level and system level of this design is completed. Developed complete test function code for host interface, and completed different levels of function verification and timing verification. It ensures that the parallel interface of the configurable host meets the requirements of design and timing constraints in function, and accomplishes the design of simulation and test platform based on C7YC68013 chip. All functions of DSP 64X HPI are verified and tested on the platform. The test results show that the designed HPI module has the correct function, the external working frequency can reach 200 MHz, and it can support the parallel transmission of 16-bit and 32-bit data, and the maximum data bandwidth can reach 800 MB. It completely meets the requirements of the overall design of the chip.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP334.7

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