本文選題：SIMD + 乘法器��； 參考：《國防科學技術大學》2013年碩士論文

【摘要】：FT-XDSP是國防科技大學自主研發(fā)的一款超長指令字結(jié)構(gòu)的64位高性能通用DSP,設計主頻1.5GHz,適用于高性能計算、無線通信、視頻和圖像處理等方面。本文依托FT-XDSP的開發(fā)與研制,旨在研究和設計面向DSP的64位高性能定點SIMD乘加部件,以滿足數(shù)字信號處理器對乘加混合運算和并行運算的處理能力。本文主要的工作和貢獻如下： 1.設計和改進了64位SIMD定點乘法器,該乘法器能夠?qū)崿F(xiàn)一個有符號和無符號64位定點乘法,或者兩個SIMD有符號或無符號32位定點乘法。該乘法器結(jié)構(gòu)采用了提前預測的思想,對符號位進行預處理來實現(xiàn)SIMD功能。經(jīng)過改進后,64位乘法器能夠同時適用于雙精度浮點53位尾數(shù)的乘法運算,而基本不影響浮點乘法的性能。改進后的乘法器在45nm工藝下的最長路徑為724ps。 2.設計并實現(xiàn)了四站流水的64位高性能定點乘加部件。該部件集成了加減法、乘法、乘加、乘減、點積、復數(shù)乘法和MOV等各種運算,并支持32位SIMD并行處理。本文設計了定點乘加部件的體系結(jié)構(gòu)和流水線,對定點乘加部件的各個流水站和關鍵模塊進行了詳細設計,包括各個流水站實現(xiàn)的功能和定點/浮點乘法器復用。并采用并行前綴加法器設計了定點乘加部件的單周期指令模塊。 3.對定點乘加部件進行了優(yōu)化、綜合與驗證。對定點乘加部件的關鍵路徑進行優(yōu)化,基于45nm工藝在Typical工作條件下對定點乘加部件進行了RC綜合,結(jié)果表明工作頻率可達1.5GHz,關鍵路徑450ps,Cell面積89727um2,功耗17.1mW。采用功能模擬驗證方法對定點乘加部件進行了詳細的模塊級驗證和DSP內(nèi)核環(huán)境下的驗證,并提出了系統(tǒng)級驗證方案。經(jīng)過驗證定點乘加部件功能正確。綜合和驗證結(jié)果表明本文的設計滿足了FT-XDSP對定點乘加部件的性能和功能設計要求。
[Abstract]:FT-X DSP is a 64 bit high performance universal DSPs with super long instruction word structure developed by the University of National Defense Science and Technology. The main frequency is 1.5GHz, which is suitable for high performance computing, wireless communication, video and image processing and so on. Based on the development and development of FT-X DSP, this paper aims to study and design 64-bit fixed-point SIMD multiplicative and additive components for DSP, so as to meet the digital signal processor's ability to deal with mixed multiplication and parallel operation. The main work and contributions of this paper are as follows: 1. A 64 bit SIMD fixed-point multiplier is designed and improved. The multiplier can implement a signed and unsigned 64-bit fixed-point multiplication, or two SIMD signed or unsigned 32-bit fixed-point multiplication. The multiplier structure adopts the idea of prediction ahead of time and preprocesses the symbol bit to realize the SIMD function. The improved 64-bit multiplier can be applied to double precision floating-point 53-bit Mantissa multiplication at the same time without affecting the performance of floating-point multiplication. The longest path of the improved multiplier in 45nm process is 724 ps.2. The 64-bit high-performance fixed-point multiplication and addition component of four-station pipeline is designed and implemented. It integrates addition and subtraction, multiplication and subtraction, dot product, complex multiplication and MOV, and supports 32-bit SIMD parallel processing. In this paper, the architecture and pipeline of fixed-point multiplication and add-ons are designed, and the pipeline stations and key modules of fixed-point multiplication are designed in detail, including the functions of each pipeline station and the multiplexing of fixed-point / floating-point multipliers. The single cycle instruction module of fixed-point multiplication and adders is designed by using parallel prefix adder. The optimization, synthesis and verification of the fixed-point multiplying and adding parts are carried out. The critical path of fixed-point multiplication and addition parts is optimized. The RC synthesis of fixed-point multiplicative parts is carried out under typical operating conditions based on 45nm process. The results show that the working frequency can reach 1.5 GHz, the critical path 450 ps-cell area 89727um2, and the power consumption 17.1 MW. The modular verification of fixed-point multiplication and the verification of DSP kernel environment are carried out by using functional simulation verification method, and a system-level verification scheme is proposed. It is verified that the function of fixed point multiplying and adding parts is correct. The results of synthesis and verification show that the design of this paper meets the performance and function design requirements of FT-X DSP for fixed-point multiplication and addition components.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332.2

【參考文獻】

相關期刊論文 前1條

1 孫Pr彥;蔣劍飛;毛志剛;;一種數(shù)字信號處理器中的高性能乘加器設計[J];微電子學;2010年01期

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本文編號：2049369