本文選題：SIMD + 乘法器�。� 參考：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：FT-XDSP是國防科技大學(xué)自主研發(fā)的一款超長指令字結(jié)構(gòu)的64位高性能通用DSP,設(shè)計(jì)主頻1.5GHz,適用于高性能計(jì)算、無線通信、視頻和圖像處理等方面。本文依托FT-XDSP的開發(fā)與研制,旨在研究和設(shè)計(jì)面向DSP的64位高性能定點(diǎn)SIMD乘加部件,以滿足數(shù)字信號處理器對乘加混合運(yùn)算和并行運(yùn)算的處理能力。本文主要的工作和貢獻(xiàn)如下： 1.設(shè)計(jì)和改進(jìn)了64位SIMD定點(diǎn)乘法器,該乘法器能夠?qū)崿F(xiàn)一個(gè)有符號和無符號64位定點(diǎn)乘法,或者兩個(gè)SIMD有符號或無符號32位定點(diǎn)乘法。該乘法器結(jié)構(gòu)采用了提前預(yù)測的思想,對符號位進(jìn)行預(yù)處理來實(shí)現(xiàn)SIMD功能。經(jīng)過改進(jìn)后,64位乘法器能夠同時(shí)適用于雙精度浮點(diǎn)53位尾數(shù)的乘法運(yùn)算,而基本不影響浮點(diǎn)乘法的性能。改進(jìn)后的乘法器在45nm工藝下的最長路徑為724ps。 2.設(shè)計(jì)并實(shí)現(xiàn)了四站流水的64位高性能定點(diǎn)乘加部件。該部件集成了加減法、乘法、乘加、乘減、點(diǎn)積、復(fù)數(shù)乘法和MOV等各種運(yùn)算,并支持32位SIMD并行處理。本文設(shè)計(jì)了定點(diǎn)乘加部件的體系結(jié)構(gòu)和流水線,對定點(diǎn)乘加部件的各個(gè)流水站和關(guān)鍵模塊進(jìn)行了詳細(xì)設(shè)計(jì),包括各個(gè)流水站實(shí)現(xiàn)的功能和定點(diǎn)/浮點(diǎn)乘法器復(fù)用。并采用并行前綴加法器設(shè)計(jì)了定點(diǎn)乘加部件的單周期指令模塊。 3.對定點(diǎn)乘加部件進(jìn)行了優(yōu)化、綜合與驗(yàn)證。對定點(diǎn)乘加部件的關(guān)鍵路徑進(jìn)行優(yōu)化,基于45nm工藝在Typical工作條件下對定點(diǎn)乘加部件進(jìn)行了RC綜合,結(jié)果表明工作頻率可達(dá)1.5GHz,關(guān)鍵路徑450ps,Cell面積89727um2,功耗17.1mW。采用功能模擬驗(yàn)證方法對定點(diǎn)乘加部件進(jìn)行了詳細(xì)的模塊級驗(yàn)證和DSP內(nèi)核環(huán)境下的驗(yàn)證,并提出了系統(tǒng)級驗(yàn)證方案。經(jīng)過驗(yàn)證定點(diǎn)乘加部件功能正確。綜合和驗(yàn)證結(jié)果表明本文的設(shè)計(jì)滿足了FT-XDSP對定點(diǎn)乘加部件的性能和功能設(shè)計(jì)要求。
[Abstract]:FT-X DSP is a 64 bit high performance universal DSPs with super long instruction word structure developed by the University of National Defense Science and Technology. The main frequency is 1.5GHz, which is suitable for high performance computing, wireless communication, video and image processing and so on. Based on the development and development of FT-X DSP, this paper aims to study and design 64-bit fixed-point SIMD multiplicative and additive components for DSP, so as to meet the digital signal processor's ability to deal with mixed multiplication and parallel operation. The main work and contributions of this paper are as follows: 1. A 64 bit SIMD fixed-point multiplier is designed and improved. The multiplier can implement a signed and unsigned 64-bit fixed-point multiplication, or two SIMD signed or unsigned 32-bit fixed-point multiplication. The multiplier structure adopts the idea of prediction ahead of time and preprocesses the symbol bit to realize the SIMD function. The improved 64-bit multiplier can be applied to double precision floating-point 53-bit Mantissa multiplication at the same time without affecting the performance of floating-point multiplication. The longest path of the improved multiplier in 45nm process is 724 ps.2. The 64-bit high-performance fixed-point multiplication and addition component of four-station pipeline is designed and implemented. It integrates addition and subtraction, multiplication and subtraction, dot product, complex multiplication and MOV, and supports 32-bit SIMD parallel processing. In this paper, the architecture and pipeline of fixed-point multiplication and add-ons are designed, and the pipeline stations and key modules of fixed-point multiplication are designed in detail, including the functions of each pipeline station and the multiplexing of fixed-point / floating-point multipliers. The single cycle instruction module of fixed-point multiplication and adders is designed by using parallel prefix adder. The optimization, synthesis and verification of the fixed-point multiplying and adding parts are carried out. The critical path of fixed-point multiplication and addition parts is optimized. The RC synthesis of fixed-point multiplicative parts is carried out under typical operating conditions based on 45nm process. The results show that the working frequency can reach 1.5 GHz, the critical path 450 ps-cell area 89727um2, and the power consumption 17.1 MW. The modular verification of fixed-point multiplication and the verification of DSP kernel environment are carried out by using functional simulation verification method, and a system-level verification scheme is proposed. It is verified that the function of fixed point multiplying and adding parts is correct. The results of synthesis and verification show that the design of this paper meets the performance and function design requirements of FT-X DSP for fixed-point multiplication and addition components.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332.2

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相關(guān)期刊論文 前1條

1 孫Pr彥;蔣劍飛;毛志剛;;一種數(shù)字信號處理器中的高性能乘加器設(shè)計(jì)[J];微電子學(xué);2010年01期

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本文編號：2049369