本文選題：多核/眾核 + 線程級(jí)猜測(cè)執(zhí)行�。� 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：多核(Multi-core)/眾核(Many-core)體系結(jié)構(gòu)已成為當(dāng)前高性能通用處理器設(shè)計(jì)時(shí)的首選。隨著工藝技術(shù)的進(jìn)步,處理器芯片中集成的計(jì)算資源和存儲(chǔ)資源越來(lái)越多,這使得以猜測(cè)的方式挖掘應(yīng)用中的粗粒度并行成為可能。不少研究工作已經(jīng)表明,猜測(cè)并行(Speculative Parallelization)機(jī)制能夠在簡(jiǎn)化并行編程模型的同時(shí),有效提高應(yīng)用程序的性能。軟件模擬一直是處理器體系結(jié)構(gòu)研究的主要手段,在當(dāng)前多核/眾核處理器體系結(jié)構(gòu)的研究中也發(fā)揮著重要作用。特別是在時(shí)間和成本受限的情況下,很多研究工作都基于軟件模擬工具進(jìn)行。然而,模擬速度慢一直是軟件模擬工具的一個(gè)重要不足。為了支持猜測(cè)并行研究,本文著重研究了如何設(shè)計(jì)并實(shí)現(xiàn)一個(gè)高效的支持線程級(jí)猜測(cè)并行的多核體系結(jié)構(gòu)軟件模擬環(huán)境,主要研究工作與成果如下:1.TLS模擬庫(kù)TLS-SL的設(shè)計(jì)與實(shí)現(xiàn)在深入分析現(xiàn)有線程級(jí)猜測(cè)執(zhí)行(Thread Level Speculation,TLS)機(jī)制和相關(guān)多核/眾核體系結(jié)構(gòu)設(shè)計(jì)的基礎(chǔ)上,定義了一個(gè)線程級(jí)猜測(cè)并行模擬庫(kù)(TLS Simulation Library,TLS-SL),我們?cè)陂_源的SESC軟件模擬器上進(jìn)行了實(shí)現(xiàn)和正確性測(cè)試。2.執(zhí)行后時(shí)序分析方法(Post-Execution Timing Analysis,PETA)為解決軟件模擬效率低的問題,本文還探索了SESC模擬器的加速方法,提出并實(shí)現(xiàn)了一種執(zhí)行后時(shí)序分析方法,有效提高了模擬速度。基于這種方法,實(shí)現(xiàn)了PETA-sim并行模擬器,在Intel多核平臺(tái)上面向Parsec基準(zhǔn)程序的測(cè)試結(jié)果證明了這種方法的正確和有效。我們的工作為進(jìn)行多核/眾核平臺(tái)下線程級(jí)猜測(cè)執(zhí)行機(jī)制的研究奠定了很好的基礎(chǔ)。
[Abstract]:Multi-Core Multi-Core / Multi-Core Many-Core (Many-Core) architecture has become the first choice in the design of high performance universal processors. With the development of process technology, more and more computing and storage resources are integrated into processor chips, which makes it possible to mine coarse-grained parallelism in applications by guessing. Many researches have shown that the speculative parallelization mechanism can effectively improve the performance of applications while simplifying the parallel programming model. Software simulation is the main method of processor architecture research, and it also plays an important role in the research of multi-core / multi-core processor architecture. Especially in the case of time and cost constraints, many research work is based on software simulation tools. However, the slow speed of simulation has always been an important deficiency of software simulation tools. In order to support the research of conjecture parallelism, this paper focuses on how to design and implement an efficient multi-core architecture software simulation environment that supports thread level conjecture parallelism. The main research work and results are as follows: 1. The design and implementation of TLS-SL, a TLS simulation library, is based on the in-depth analysis of the existing Thread level SpeculationTLSs mechanism and the related multi-core / crowdcore architecture design. A thread level conjecture parallel simulation library, TLS Simulation Library, TLS-SLN, is defined. We have carried out implementation and correctness testing on the open source SESC software simulator. Post-execution timing Analysis (PETAA). In order to solve the problem of low efficiency of software simulation, this paper also explores the acceleration method of SESC simulator, and proposes and implements a post-execution timing analysis method, which effectively improves the simulation speed. Based on this method, PETA-sim parallel simulator is implemented. The test results for Parsec benchmark program on Intel multi-core platform show that this method is correct and effective. Our work lays a good foundation for the research of the execution mechanism of thread level guesses in multi-core / multi-kernel platform.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
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本文編號(hào)：2047501