本文選題：MPSoC + 通訊架構(gòu)��； 參考：《南京大學(xué)》2012年碩士論文

【摘要】：片上多核系統(tǒng)MPSoC(Multiprocessor System-on-Chip)能夠充分利用多處理器的數(shù)據(jù)并行處理能力以及SoC的高集成度,針對目標應(yīng)用的多樣性進行定制化的設(shè)計,從而使系統(tǒng)的硬件結(jié)構(gòu)更好地滿足目標應(yīng)用的需求,能夠最大限度地提升系統(tǒng)的整體性能。眾多MPSoC通訊架構(gòu)地提出,為滿足復(fù)雜應(yīng)用的大規(guī)模運算和實時性需求提供了可行的解決辦法,正逐漸演變?yōu)槎嗵幚砥飨到y(tǒng)和下一代集成電路設(shè)計的主流趨勢。 本文描述和分析了MPSoC基本通訊架構(gòu)模型,提出了一種多核初始化方案。該方案將Flash存儲器連接到片上通訊網(wǎng)絡(luò)的通訊節(jié)點上作為初始化數(shù)據(jù)源,采用發(fā)送網(wǎng)絡(luò)數(shù)據(jù)包的方式逐一對多核系統(tǒng)中的多個處理器核進行初始化,同時采用引導(dǎo)程序與用戶主程序分開設(shè)計的方法,使得引導(dǎo)程序的設(shè)計具有較好的獨立性和可移植性。設(shè)計中的Flash Wrapper模塊完成從Flash接口協(xié)議到PCC協(xié)議的轉(zhuǎn)化,依靠狀態(tài)機來實現(xiàn)鏈路的建立和數(shù)據(jù)的傳輸,同時給予實驗,實現(xiàn)每個簇中核的初始化。此外對Rocket10進行了介紹和分析,并簡述了Aurora協(xié)議以及8b/10b編解碼,在此基礎(chǔ)上設(shè)計了基于多核芯片數(shù)據(jù)傳輸?shù)腞ocket10Wrapper,實現(xiàn)數(shù)據(jù)的高速傳輸�；赬ilinx的FPGA開發(fā)平臺,我們對整個系統(tǒng)進行了FPGA原型實現(xiàn),分步驗證模塊設(shè)計與數(shù)據(jù)傳輸。
[Abstract]:Multi-core system MPSoC / Multiprocessor System-on-Chip (MPSoC) can make full use of the multi-processor data parallel processing ability and the high integration of SoC, and can customize the diversity of target applications. Thus, the hardware structure of the system can better meet the requirements of the target application, and the overall performance of the system can be greatly improved. Many MPSoC communication architectures are proposed, which provide a feasible solution to meet the needs of large-scale computing and real-time of complex applications, and are gradually becoming the mainstream trend of multi-processor systems and next-generation integrated circuit design. This paper describes and analyzes the MPSoC basic communication architecture model and proposes a multi-core initialization scheme. In this scheme, Flash memory is connected to the communication node of the communication network on chip as the initialization data source, and the multi-processor cores in the multi-core system are initialized by sending the network data packets. At the same time, the bootstrap program is designed separately from the user's main program, which makes the bootstrap design more independent and portable. The Flash wrapper module is designed to realize the conversion from Flash interface protocol to PCC protocol. The state machine is used to realize the link establishment and data transmission. At the same time, the experiment is carried out to initialize the core in each cluster. In addition, Rocket10 is introduced and analyzed, and the Aurora protocol and 8b/10b codec are briefly described. On this basis, Rocket10Wrapper-based multi-core chip data transmission is designed to realize high-speed data transmission. Based on the FPGA development platform of Xilinx, we implemented the whole system with FPGA prototype, step by step verification module design and data transmission.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2012
【分類號】：TP332;TN47

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